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131. 发明专利

JPH08153778A MANUFACTURE OF SEMICONDUCTOR DEVICE HAVING SOI STRUCTURE 失效
公开(公告)号：JPH08153778A
公开(公告)日：1996-06-11
申请号：JP29269794
申请日：1994-11-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , INOUE YASUAKI
IPC分类号： H01L21/32 , H01L21/322 , H01L21/336 , H01L21/76 , H01L21/762 , H01L27/08 , H01L27/12 , H01L29/786
摘要： PURPOSE: To prevent occurrent of a parasitic MOS transistor at the end section of the SOI layer of a semiconductor device having an SOI structure. CONSTITUTION: After a buried oxide film 2 and SOI layers 3 are respectively formed on the main surface of a substrate, nitride films 21 patterned to prescribed shapes are respectively formed on the SOI layers 3. After forming the SOI layers 3, a first selective oxidizing process is performed on the SOI layers 3 by using the nitride films 21 as masks. The separating oxide films 4a formed by the selective oxidizing process is prevented from reaching the buried oxide film 2. Then the oxide films 4a are subjected to anisotropic etching by using the films 21 as masks and side wall insulating layers 28 composed of an oxidation-resistant substance are formed on the side walls of the nitride films 21. Finally, a separating oxide film 4 is formed by performing second selective oxidizing process on the SOI layers 3 by using the insulating layers 28 and nitride films 21 as masks.

132. 发明专利

JPH07221297A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07221297A
公开(公告)日：1995-08-18
申请号：JP884094
申请日：1994-01-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , INOUE YASUAKI , YAMAGUCHI YASUO , NISHIMURA TADASHI
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/78 , H01L29/786
摘要： PURPOSE:To reduce parasitic resistance of a source region and a drain region and, especially, to reduce the parasitic resistance of the source region more than the parasitic resistance of the drain region. CONSTITUTION:Inert impurities are implanted into only a source region 8a in a semiconductor layer. A crystalline damaged layer is formed near the surface of the semiconductor layer. Thereby, a reaction to form a silicide is promoted smoothly, and a thick titanium silicide film 15 is formed in the source region 8a.

133. 发明专利

JPH06140631A FIELD-EFFECT THIN FILM TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH06140631A
公开(公告)日：1994-05-20
申请号：JP29029392
申请日：1992-10-28
申请人： RYODEN SEMICONDUCTOR SYST ENG , MITSUBISHI ELECTRIC CORP
发明人： NISHIMURA TSUNEYUKI , SUGAHARA KAZUYUKI , MAEDA SHIGENOBU , IPPOSHI TAKASHI , INOUE YASUAKI , IWAMATSU TOSHIAKI , IKEDA MIKIO , KUNIKIYO TATSUYA , TATEISHI JUNJI , MINATO TADAKURO
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/786 , H01L29/784
摘要： PURPOSE:To obtain a field-effect thin film transistor(TFT) which stabilizes read and write operations of a memory cell and reduces power consumption in a micro-miniaturized TFT load type perfect CMOS.SRAM. CONSTITUTION:A field-effect thin film transistor formed on an insulating material is provided with an active layer 55 and a gate electrode 60. The gate electrode 60 is formed on a channel region 55a of the active layer 55 through a gate insulating film. The active layer 55 is composed of the channel region 55a and a source drain region 55b. The channel region 55a does not include crystal grain boundary formed of a single crystal silicon layer and the source drain region 55b is formed of polycrystalline silicon layer. Moreover, the channel region 55a has a crystal defect density under 10 pcs/cm . The thin film transistor shows an ON current of 0.25 muA/mum or more and an OFF current of 15fA/mum or less per the channel width of 1mum.

134. 发明专利

JPH05198739A LAMINATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH05198739A
公开(公告)日：1993-08-06
申请号：JP16459392
申请日：1992-06-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUGAHARA KAZUYUKI , IWAMATSU TOSHIAKI , IPPOSHI TAKASHI , AJIKA NATSUO , OGAWA TOSHIAKI
IPC分类号： H01L27/00 , H01L21/02 , H01L21/20 , H01L21/762 , H01L21/822 , H01L27/12 , H01L29/78 , H01L29/786
摘要： PURPOSE:To produce a laminated semiconductor device without a bad influence on the device characteristics, by sticking substrates to each other by heat treatment at a comparatively low temperature. CONSTITUTION:A first semiconductor substrate 51 with a first device is covered with an interlayer insulating layer 57, and a flat polycrystal silicon layer 58 is formed on it. And the first semiconductor substrate 51 and a second semiconductor substrate 59 are joined and fixed, by closely sticking the surface of a high-melting point metal layer 61 formed on the second semiconductor substrate to the surface of the above-mentioned polycrystal silicon layer 58, performing a heat treatment of 700 deg.C or lower, and turning the high-melting point metal layer 61 into a silicide.

135. 发明专利

JPH04259249A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04259249A
公开(公告)日：1992-09-14
申请号：JP2073591
申请日：1991-02-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , ONODA HIROSHI , OGAWA TOSHIAKI
IPC分类号： H01L25/18 , H01L21/02 , H01L21/027 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/12
摘要： PURPOSE:To improve integration by providing a second alignment mark formed on a predetermined region except a region formed with a first alignment mark on a semiconductor layer to be rotated at 180 degrees to the first mark and formed in a mirrorinversion. CONSTITUTION:First alignment marks 1001, 1002 are used for a mask alignment at the time of forming an NMOSFET/SOI on an insulating film 2. Second alignment marks 1003, 1004 are used for a mask alignment at the time of forming a PMOSFET/SOI under the film 2. A semiconductor layer is formed on one main surface of the film 2, the marks 1001, 1002 are formed on a predetermined region on the layer, and the marks 1003, 1004 are formed to be rotated at 180 degrees to the marks 1001, 1002 and mirror-inverted on a predetermined region except the region formed with the marks 1001, 1002 on the layer.

136. 发明专利

JPH04196264A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04196264A
公开(公告)日：1992-07-16
申请号：JP33294790
申请日：1990-11-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUGAHARA KAZUYUKI , IWAMATSU TOSHIAKI , IPPOSHI TAKASHI
IPC分类号： H01L27/00 , H01L29/786
摘要： PURPOSE:To make it possible to manufacture a laminated semiconductor device of a large integration degree by a method wherein a device is formed on an insulator and thereafter, a support substrate is laminated on the device, the rear of a water is polished and a device is formed on a left semiconductor layer. CONSTITUTION:An N MOSFET (A) is formed on a base insulating film 22 on a single crystal silicon substrate 11. Then, a BPSG film 51a is deposited on the N MOSFET, an annealing is performed to flatten the surface of the film 51a and moreover, another single crystal silicon substrate 14 is prepared, a BPSG film 51b is deposited on this substrate 14, the substrate 14 with its surface flattened by an annealing is prepared, the support substrate 14 is pressure bonded on the substrate 11 with the N MOSFET (A) formed thereon and the substrate 14 is laminated on the substrate 11 by a heat treatment. The bottom of the substrate 11 is polished as the reference of a polishing surface, then, the substrate 14 is faced downward, a signal crystal silicon film 15 is patterned and a P MOSFET (B) is formed on the N MOSFET (A). Thereby, the superposition accuracy of devices on upper and lower layers is improved and moreover, the integration degree of a laminated semiconductor device can be enhanced.

137. 发明专利

JP2003318405A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003318405A
公开(公告)日：2003-11-07
申请号：JP2002124180
申请日：2002-04-25
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MAEDA SHIGENOBU , MATSUMOTO TAKUJI , IWAMATSU TOSHIAKI , IPPOSHI TAKASHI
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7841 , H01L29/78615 , H01L29/78654 , Y10S438/981
摘要： PROBLEM TO BE SOLVED: To provide a SOI device where a body is fixed and a high speed and stable operation is realized. SOLUTION: A gate insulating film 11 whose thickness is 1 to 5 nm is disposed between a part except for a gate contact pad GP in a gate electrode 12 and a SOI layer 3. A gate insulating film 110 whose thickness is 5 to 15 nm is arranged between the gate contact pad GP and the SOI layer 3. The gate insulating film 11 and the gate insulating film 110 continue. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种身体固定并实现高速稳定操作的SOI器件。解决方案：栅极电极12和SOI层3之间的栅极接触焊盘GP之外的部分之间设置厚度为1〜5nm的栅极绝缘膜11.栅极绝缘膜110的厚度为5〜在栅极接触焊盘GP和SOI层3之间设置15nm。栅极绝缘膜11和栅极绝缘膜110继续。版权所有（C）2004，JPO

138. 发明专利

JP2003101030A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：JP2003101030A
公开(公告)日：2003-04-04
申请号：JP2001299863
申请日：2001-09-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUMOTO TAKUJI , SAYAMA HIROKAZU , MAEDA SHIGENOBU , IWAMATSU TOSHIAKI , OTA KAZUNOBU
IPC分类号： H01L21/822 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H04L1/16 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device, in which the gain of a parasitic bipolar transistor is reduced to suppress malfunctioning and the fluctuation of operation characteristics, and to obtain a method of manufacturing a semiconductor device. SOLUTION: A silicon oxide film 6 is partially formed on the upper surface of a silicon layer 3. A gate electrode 7 made of polycrystalline silicon is partially formed on the silicon oxide film 6. The part of the silicon oxide film 6 located under the gate electrode 7 functions as a gate insulation film. A silicon nitride film 9 is formed on the side surface of the gate electrode 7 with a silicon oxide film 8 sandwiched in between. The silicon oxide film 8 and the silicon nitride film 9 are formed on the silicon oxide film 6. The width W1, in the longitudinal direction of the gate, is larger than thickness T1 of the silicon oxide film 6.

139. 发明专利

JP2001339071A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001339071A
公开(公告)日：2001-12-07
申请号：JP2000342937
申请日：2000-11-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： HIRANO YUICHI , MAEKAWA SHIGETO , IWAMATSU TOSHIAKI , MATSUMOTO TAKUJI , MAEDA SHIGENOBU , YAMAGUCHI YASUO
IPC分类号： H01L21/762 , H01L21/3205 , H01L21/76 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/52 , H01L27/04 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device for inhibiting the fluctuation of the potential of a body region caused by the fluctuation of the potential of power supply wiring. SOLUTION: A partial-trench element isolation insulating film 5 is selectively formed in the upper surface of a silicon layer 4. Power supply wiring 21 is formed at the upper portion of the element isolation insulating film 5. At the upper portion of the power supply wiring 21, a complete isolation part 23 to the upper surface of the insulating layer 3 is formed at the element isolation insulating film 5. In other words, this semiconductor device is provided with a complete-isolation-type element isolation insulating film that is formed from the upper surface of the silicon layer 4 to the upper surface of the insulating layer 3 at the lower portion of the power supply wiring 21.

140. 发明专利

JP2001230315A SEMICONDUCTOR DEVICE AND ITS FABRICATING METHOD 失效
公开(公告)号：JP2001230315A
公开(公告)日：2001-08-24
申请号：JP2000039484
申请日：2000-02-17
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , IPPOSHI TAKASHI , MATSUMOTO TAKUJI
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including an MOS transistor, and its fabricating method, in which a gate oxide film is protected against dielectric breakdown without increasing the thickness thereof. SOLUTION: A merged isolation oxide film BT1 has a part on the gate electrode GT13 side penetrating an SOI layer 3 to reach a buried oxide film 2 and a part on the gate electrode GT12 side having such a cross-section as a well region is provided below. The merged isolation oxide film BT1 has a bird's beak like end edge part in an LOCOS isolation oxide film. Consequently, the end edge parts of gate oxide films GO12 and GO13 are made thick locally.

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