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131. 发明申请

US20090294982A1 INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES 有权
标题翻译：具有由两个光刻过程产生的三维特征的互连结构
公开(公告)号：US20090294982A1
公开(公告)日：2009-12-03
申请号：US12538114
申请日：2009-08-08
申请人： Matthew E. Colburn , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman
发明人： Matthew E. Colburn , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman
IPC分类号： H01L23/522
CPC分类号： H01L23/53238 , H01L21/76801 , H01L21/76808 , H01L21/76816 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.
摘要翻译：一种制造互连结构的方法，用于将半导体衬底互连以具有三个不同的图案化结构，使得互连结构既提供低k和高结构完整性。该方法包括在半导体衬底上沉积层间电介质，通过第一光刻工艺在层间电介质材料内形成第一图案，该第一光刻工艺导致在互连结构中形成通孔特征和三元特征。该方法还包括通过第二光刻工艺在层间电介质材料内形成第二图案以在互连结构内形成线特征。因此，该方法仅对每个互连级别仅使用两个光刻工艺形成三个独立的不同图案结构。

132. 发明授权

US07517637B2 Method of producing self-aligned mask in conjunction with blocking mask, articles produced by same and composition for same 失效
标题翻译：生产自对准面罩的方法与阻隔面罩相同，制成的物品及其成分相同
公开(公告)号：US07517637B2
公开(公告)日：2009-04-14
申请号：US10804552
申请日：2004-03-19
申请人： Matthew E Colburn , Satyanarayana V Nitta , Sampath Purushothaman
发明人： Matthew E Colburn , Satyanarayana V Nitta , Sampath Purushothaman
IPC分类号： G03F7/00
CPC分类号： G03F7/2022
摘要： A method of forming a self aligned pattern on an existing pattern on a substrate including applying a coating of a solution containing a masking material in a carrier, the masking material being either photo or thermally sensitive; performing a blanket exposure of the substrate; and allowing at least a portion of the masking material to preferentially develop in a fashion that replicates the existing pattern of the substrate. The existing pattern includes a first set of regions of the substrate having a first reflectivity and a second set of regions of the substrate having a second reflectivity different from the first composition. The first set of regions can include one or more metal elements and the second set of regions can include one or more dielectrics. Structures made in accordance with the method. A low resolution mask is used to block out regions over the substrate. Additionally, the resist can be applied over another masking layer that contains a separate pattern.
摘要翻译：一种在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩模材料的溶液的涂层，所述掩模材料为光敏或热敏感的; 进行基板的覆盖曝光; 并且允许至少一部分掩模材料以复制衬底的现有图案的方式优先显影。现有图案包括具有第一反射率的衬底的第一组区域和具有不同于第一组成的第二反射率的衬底的第二组区域。第一组区域可以包括一个或多个金属元素，第二组区域可以包括一个或多个电介质。按照该方法制造的结构。低分辨率掩模用于阻挡衬底上的区域。另外，抗蚀剂可以施加在包含单独图案的另一掩蔽层上。

133. 发明申请

US20090033360A1 PROGRAMMABLE VIA DEVICES WITH AIR GAP ISOLATION 有权
标题翻译：可通过具有空气隔离的装置进行编程
公开(公告)号：US20090033360A1
公开(公告)日：2009-02-05
申请号：US11833354
申请日：2007-08-03
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Dennis M. Newns , Sampath Purushothaman
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Dennis M. Newns , Sampath Purushothaman
IPC分类号： H03K19/177 , H01L45/00
CPC分类号： H01L45/06 , H01L28/20 , H01L45/1206 , H01L45/122 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.
摘要翻译：提供可编程的器件及其制造方法。在一个方面，提供了可编程通路装置。可编程通孔装置包括第一介电层; 第一介电层上的加热器; 将所述加热器的至少一部分与所述第一介电层分开的气隙; 覆盖所述加热器的至少一部分的所述第一介电层上的隔离层; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

134. 发明申请

US20090033358A1 PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL 有权
标题翻译：通过线路后端的设备可编程
公开(公告)号：US20090033358A1
公开(公告)日：2009-02-05
申请号：US11833321
申请日：2007-08-03
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Dennis M. Newns , Sampath Purushothaman
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Dennis M. Newns , Sampath Purushothaman
IPC分类号： H01L45/00 , H03K19/177
CPC分类号： H01L28/65 , H01L28/20 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683 , Y10S977/754
摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.
摘要翻译：提供可编程的器件及其制造方法。在一个方面，提供了可编程通路装置。可编程通孔装置包括第一介电层; 在所述第一介电层上方的至少一个隔离层; 隔离层内的加热器; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

135. 发明申请

US20070249156A1 METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY 审中-公开
标题翻译：用于实现超低K材料和生产的结构的硬掩模自由集成的方法
公开(公告)号：US20070249156A1
公开(公告)日：2007-10-25
申请号：US11672608
申请日：2007-02-08
申请人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
发明人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
IPC分类号： H01L21/4763
CPC分类号： H01L21/76826 , H01L21/02074 , H01L21/3105 , H01L21/31058 , H01L21/76883
摘要： A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an etch stop and barrier layer. In situ reaction of the damaged regions with a suitable silylation agent just prior to a passivation barrier cap deposition is proposed as the most efficacious means to repair all the damage sustained by the dielectric. Variations of this method which include ex situ rather than in situ silylation are also described for use with hard mask free integration with selective barrier caps.
摘要翻译：描述了一种用于修复由低k有机硅酸盐电介质持续的过程诱导的损伤作为反应离子蚀刻，抗蚀剂条，湿清洁和CMP操作在将这些电介质纳入包含电介质的微电子互连结构的硬掩模中的CMP操作的方法盖是蚀刻停止层和阻挡层。在钝化阻挡层沉积之前，损伤区域与合适的甲硅烷基化剂的原位反应被提出作为修复由电介质所承受的所有损伤的最有效手段。还描述了包括异位原位甲硅烷基化的这种方法的变化，用于与选择性屏障帽的硬掩模自由积分。

136. 发明申请

US20060267208A1 Method of forming closed air gap interconnects and structures formed thereby 失效
标题翻译：形成闭合气隙互连件和由此形成的结构的方法
公开(公告)号：US20060267208A1
公开(公告)日：2006-11-30
申请号：US11405283
申请日：2006-04-17
申请人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
发明人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.
摘要翻译：描述了形成闭合气隙互连结构的方法。在互连线下方由永久支撑电介质的区域构成的起始结构和在互连结构的其余部分中存在的具有一个或多个牺牲电介质的周围的互连通孔被封装有电介质阻挡层，其使用具有规则的模板孔阵列然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。描述该方法的几个实施例和所得到的结构。

137. 发明授权

US07030481B2 High density chip carrier with integrated passive devices 有权
标题翻译：具有集成无源器件的高密度芯片载体
公开(公告)号：US07030481B2
公开(公告)日：2006-04-18
申请号：US10314589
申请日：2002-12-09
申请人： Michael Patrick Chudzik , Robert H. Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph F. Shepard, Jr. , Anna Wanda Topol
发明人： Michael Patrick Chudzik , Robert H. Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph F. Shepard, Jr. , Anna Wanda Topol
IPC分类号： H01L23/053
CPC分类号： H05K1/162 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/157 , H01L2924/30105 , H05K1/167 , H05K3/4602 , H05K2201/09809
摘要： A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.
摘要翻译：提供了一种用于半导体部件的载体，其具有集成在其基板中的无源部件。无源组件包括去耦组件，例如电容器和电阻器。一组连接被集成以提供与受支持的部件的紧密的电气接近。

138. 发明授权

US06943451B2 Semiconductor devices containing a discontinuous cap layer and methods for forming same 有权
标题翻译：包含不连续盖层的半导体器件及其形成方法
公开(公告)号：US06943451B2
公开(公告)日：2005-09-13
申请号：US09897200
申请日：2001-07-02
申请人： Stanley Joseph Whitehair , Stephen McConnell Gates , Sampath Purushothaman , Satyanarayana V. Nitta , Maurice McGlashan-Powell , Kevin S. Petrarca
发明人： Stanley Joseph Whitehair , Stephen McConnell Gates , Sampath Purushothaman , Satyanarayana V. Nitta , Maurice McGlashan-Powell , Kevin S. Petrarca
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L21/4763 , H01L23/52 , H01L23/58 , H01L29/40
CPC分类号： H01L21/76888 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.
摘要翻译：本文提供了包含不连续盖层并且具有相对低介电常数的新型半导体器件。新颖的半导体器件至少包括衬底，施加在衬底的至少一部分上的第一介电层，通过电介质层形成的第一组开口，以暴露衬底的表面，使得沉积在其中并填充的导电材料开口提供第一组电接触导电元件和覆盖至少导电元件的顶部的不连续的覆盖材料层，以提供第一组不连续帽元件。还提供了形成半导体器件的方法。

139. 发明申请

US20050082526A1 Techniques for layer transfer processing 审中-公开
标题翻译：层转移处理技术
公开(公告)号：US20050082526A1
公开(公告)日：2005-04-21
申请号：US10685636
申请日：2003-10-15
申请人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
发明人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
IPC分类号： H01L21/00 , H01L21/762 , H01L29/04
CPC分类号： H01L21/76259 , Y10T428/249961
摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided.
摘要翻译：提供了制造半导体器件的技术。一方面，提供了层转移结构。层转移结构包括具有调节孔隙度的多孔区域的载体衬底和在其中限定分离平面的注入物质的组合。另一方面，提供了一种形成层转移结构的方法。另一方面，提供一种形成三维一体化结构的方法。

140. 发明授权

US06780499B2 Ordered two-phase dielectric film, and semiconductor device containing the same 有权
标题翻译：有序的两相电介质膜，以及包含它的半导体器件
公开(公告)号：US06780499B2
公开(公告)日：2004-08-24
申请号：US09848153
申请日：2001-05-03
申请人： Stephen McConnell Gates , Christopher B. Murray , Satyanarayana V. Nitta , Sampath Purushothaman
发明人： Stephen McConnell Gates , Christopher B. Murray , Satyanarayana V. Nitta , Sampath Purushothaman
IPC分类号： B32B518
CPC分类号： H01L21/02112 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02304 , H01L21/31695 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , Y10T428/24149 , Y10T428/24917 , Y10T428/249953 , Y10T428/249958 , Y10T428/249967 , Y10T428/249969 , Y10T428/249978 , Y10T428/249979 , Y10T428/249987 , Y10T428/24999 , Y10T428/249991 , Y10T428/26 , Y10T428/31663 , H01L2924/00
摘要： A porous, low-k dielectric film that has good mechanical properties as well as a method of fabricating the film and the use of the film as a dielectric layer between metal wiring features are provided. The porous, low-k dielectric film includes a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice; and a second phase which is solid surrounding the first phase. Specifically, the second phase of the film includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of a dielectric material having a dielectric constant of about 2.8 or less.
摘要翻译：提供具有良好机械性能的多孔，低k电介质膜以及制造膜的方法以及该膜用作金属布线特征之间的介电层。多孔低k电介质膜包括直径为约1至约10nm的单分散孔的第一相，其基本均匀间隔开并且基本上位于三维周期性晶格的位置上; 以及围绕第一相的固体的第二相。具体地，膜的第二相包括（i）由具有约1至约10nm的直径的纳米颗粒组成的有序元件，其基本上均匀间隔开并且基本上布置在三维周期晶格的位置，和（ii）由介电常数为约2.8或更小的介电材料组成的无序元件。

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