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    • 139. 发明授权
    • Cache directed sequential prefetch
    • 缓存定向顺序预取
    • US08458408B2
    • 2013-06-04
    • US13023615
    • 2011-02-09
    • William E. SpeightLixin Zhang
    • William E. SpeightLixin Zhang
    • G06F12/00
    • G06F12/0862G06F2212/6026
    • A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream.
    • 用于在高速缓冲存储器内执行流检测和预取的技术简化了流检测和预取。 高速缓存目录或高速缓存条目中的一点表示高速缓存行未被访问,并且另一位指示与高速缓存行相关联的流的方向。 当先前预取的高速缓存行被访问时,预取下一个高速缓存行,使得高速缓存总是尝试在检测到的流的方向上预取访问之前的一个高速缓存行。 响应于在负载未命中队列(LMQ)中跟踪的加载未命中,执行流检测。 LMQ存储指示高速缓存行内的偏移处的第一个未命中的偏移。 下一个未命中的线路将基于第一和第二个偏移量之间的差异设置方向位,并导致流的下一行的预取。