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131. 发明申请

US20130176771A1 8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES 有权
标题翻译：具有外部门极二极管的8晶体管SRAM单元设计
公开(公告)号：US20130176771A1
公开(公告)日：2013-07-11
申请号：US13345636
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C16/24 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译：一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

132. 发明申请

US20130175597A1 NANOWIRE FLOATING GATE TRANSISTOR 有权
标题翻译： NANOWIRE浮动门极晶体管
公开(公告)号：US20130175597A1
公开(公告)日：2013-07-11
申请号：US13344517
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： G11C11/5671 , H01L21/28273 , H01L29/0673 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.
摘要翻译：浮栅晶体管，存储单元及其制造方法。浮栅晶体管包括一个或多个基本上圆柱形的选通线。浮置栅极晶体管包括至少部分地覆盖选通导线的第一栅极电介质层。浮置栅极晶体管还包括不连续地布置在第一栅极介电层上的多个栅极晶体。浮栅晶体管还包括覆盖多个栅极晶体和第一栅极介电层的第二栅极电介质层。

133. 发明申请

US20130153996A1 HYBRID CMOS NANOWIRE MESH DEVICE AND PDSOI DEVICE 有权
标题翻译： HYBRID CMOS NANOWIRE MESH DEVICE和PDSOI DEVICE
公开(公告)号：US20130153996A1
公开(公告)日：2013-06-20
申请号：US13328069
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/088 , H01L21/28 , H01L29/78 , B82Y40/00 , B82Y99/00
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和PDSOI器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和PDSOI器件的半导体结构。

134. 发明授权

US08445337B2 Generation of multiple diameter nanowire field effect transistors 有权
标题翻译：生成多直径纳米线场效应晶体管
公开(公告)号：US08445337B2
公开(公告)日：2013-05-21
申请号：US12778517
申请日：2010-05-12
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/0669 , B82Y10/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.
摘要翻译：提供了一种修改具有设置在绝缘体上的半导体的晶片的方法，包括以不同的初始半导体厚度建立晶片的第一和第二区域，形成经由每个第一和第二区域上的相应纳米线通道连接的半导体焊盘对，并重塑纳米线通道进入纳米线，每个纳米线具有反映第一和第二区域中的每一个处的不同初始半导体厚度的各自不同的厚度。

135. 发明授权

US08441043B2 Maskless process for suspending and thinning nanowires 失效
标题翻译：用于悬浮和稀化纳米线的无掩模工艺
公开(公告)号：US08441043B2
公开(公告)日：2013-05-14
申请号：US13006833
申请日：2011-01-14
申请人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02667 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696 , Y10S977/762
摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
摘要翻译：提供了基于半导体的电子器件及其制造技术。在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度由硅从纳米线重新分配到焊盘。该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

136. 发明申请

US20130062709A1 Gap-Fill Keyhole Repair Using Printable Dielectric Material 失效
标题翻译：使用可印刷介质材料进行缺陷孔眼修复
公开(公告)号：US20130062709A1
公开(公告)日：2013-03-14
申请号：US13232293
申请日：2011-09-14
申请人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/51 , H01L21/311 , H01L21/76825 , H01L21/76837 , H01L29/66545
摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.
摘要翻译：在半导体衬底上形成一次性栅极结构。平坦化电介质层沉积在一次性栅极结构上并且被平坦化以提供与一次性栅极结构的顶表面共面的顶表面。此时的平坦化电介质层包括狭缝间隔一次性栅极结构之间的间隙填充键孔。在平坦化介电层上沉积可印刷介电层以填充间隙填充键孔。在间隙填充键孔上的可印刷电介质层的区域被可印刷介电层的材料中交叉连接的辐射辐射照射。可打印介电层的非交联部分随后被选择性地移除到可印刷介电层的交联部分，该可印刷电介质层至少填充每个栅极填充孔眼的上部。去除一次性门结构以形成门腔。栅极腔填充有栅极电介质和栅电极。

137. 发明申请

US20130017673A1 GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS 有权
标题翻译：多直径纳米场效应晶体管的生成
公开(公告)号：US20130017673A1
公开(公告)日：2013-01-17
申请号：US13610223
申请日：2012-09-11
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/84 , B82Y99/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/302 , H01L21/3247 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.
摘要翻译：提供了修改具有设置在绝缘体上的半导体的晶片的方法，并且包括分别在第一和第二晶片区域处形成分别连接到半导体焊盘的第一和第二纳米线通道，其中第二纳米线通道侧壁相对于晶体学不对准半导体的平面超过第一纳米线通道侧壁并将半导体移向侧壁和结晶平面之间的对准状态，使得第一和第二纳米线通道之间的厚度差异反映了第二纳米线通道侧壁的较大的未对准。

138. 发明申请

US20120292598A1 EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS 有权
标题翻译：外延源/漏极触点自定义到沉积FET通道的栅极
公开(公告)号：US20120292598A1
公开(公告)日：2012-11-22
申请号：US13565342
申请日：2012-08-02
申请人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/775
CPC分类号： H01L51/0545 , B82Y10/00 , H01L27/283 , H01L51/0012 , H01L51/0048 , H01L51/0525
摘要： A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
摘要翻译：提供了一种形成自对准器件的方法，包括将碳纳米管（CNT）沉积到晶体介质衬底上，隔离包含CNT位置的晶体介质衬底的一部分，在栅极电介质层和栅电极栅叠层 CNT同时保持其结构完整性，并且形成外延源极和漏极区域，其与从栅极介电层和栅电极栅极叠层暴露的晶体介质衬底上的CNT的部分接触。

139. 发明授权

US08313990B2 Nanowire FET having induced radial strain 有权
标题翻译：纳米线FET引起径向应变
公开(公告)号：US08313990B2
公开(公告)日：2012-11-20
申请号：US12631203
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/7845 , H01L29/78696
摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
摘要翻译：提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。

140. 发明申请

US20120286242A1 NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES 有权
标题翻译： NANOWIRE PIN TUNNEL场效应器件
公开(公告)号：US20120286242A1
公开(公告)日：2012-11-15
申请号：US13556300
申请日：2012-07-24
申请人： Sarunya Bangsaruntip , Stephen J. Koester , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Stephen J. Koester , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L21/047 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/42312 , H01L29/66356 , H01L29/7391
摘要： A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion.
摘要翻译：纳米线隧道器件包括通过第一焊盘区域和第二焊盘区域悬置在半导体衬底上方的纳米线，所述纳米线具有由围绕纳米线周向设置的栅极结构围绕的沟道部分，n型掺杂区域，包括第一部分和与沟道部分相邻的纳米线的第二部分的p型掺杂区域。

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