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121. 发明公开

EP2888672A1 SYSTEM WITH PHYSICAL DATA AUTHORIZATION 审中-公开
标题翻译：系统麻省理工学院DATENAUTORISIERUNG
公开(公告)号：EP2888672A1
公开(公告)日：2015-07-01
申请号：EP14763688.0
申请日：2014-03-14
申请人： Acco Brands Corporation
发明人： LI, Qiumin , LEE, Samson
IPC分类号： G06F15/16
CPC分类号： G06F21/34 , G06F13/4068 , H02J7/0004 , H02J2007/006 , H04L7/0004 , H04L63/0853 , H04L67/1095
摘要： A system for enabling data syncing between a host device and an electronic device includes a first port configured to be coupled to a first electronic device, a second port configured to be coupled to the host device, and a data sync switch coupled to the first port and the second port. The data sync switch is switchable between a first state, in which data communication between the electronic device and the host device is enabled, and a second state, in which data communication between the electronic device and the host device is disabled. The system also includes an authorization device configured to couple to an authorizing physical object and generate an output signal. The data sync switch is in one of the first state and the second state based on the output signal from the authorization device.
摘要翻译：一种用于启用主机设备和电子设备之间的数据同步的系统包括被配置为耦合到第一电子设备的第一端口，被配置为耦合到主机设备的第二端口以及耦合到第一端口的数据同步开关和第二个港口。数据同步开关可以在电子设备和主机设备之间的数据通信被使能的第一状态和电子设备与主机设备之间的数据通信被禁用的第二状态之间切换。该系统还包括被配置为耦合到授权物理对象并生成输出信号的授权设备。数据同步开关基于来自授权装置的输出信号处于第一状态和第二状态之一。

122. 发明授权

EP2137873B1 DISPOSITIF D'EXTRACTION D'HORLOGE A ASSERVISSEMENT NUMERIQUE DE PHASE SANS REGLAGE EXTERNE 失效
标题翻译：用于在没有外部调整的情况下用相位数字增强提取时钟的装置
公开(公告)号：EP2137873B1
公开(公告)日：2014-07-09
申请号：EP08787918.5
申请日：2008-04-04
申请人： Centre National d'Etudes Spatiales (C.N.E.S.)
发明人： PIGNOL, Michel , NEVEU, Claude , DEVAL, Yann , BEGUERET, Jean-Baptiste , MAZOUFFRE, Olivier
IPC分类号： H04L7/027 , H04L7/033 , H03L7/24
CPC分类号： H03L7/083 , H03L7/089 , H03L7/091 , H04L7/0004 , H04L7/0276 , H04L7/0331

123. 发明公开

EP2745456A2 SCHALTUNGSANORDNUNG UND VERFAHREN ZUM UEBERTRAGEN VON SIGNALEN 有权转让
公开(公告)号：EP2745456A2
公开(公告)日：2014-06-25
申请号：EP12812148.0
申请日：2012-08-16
申请人： Silicon Line GmbH
发明人： BLON, Thomas , SUTTORP, Thomas , HOELTKE, Holger
IPC分类号： H04L7/00 , H04L7/10 , H04J3/22
CPC分类号： G06F13/4295 , G06F1/04 , G06F3/1454 , H04J3/0602 , H04L7/0004 , H04L7/10
摘要： The invention relates to a circuit arrangement (A) and to a corresponding method which use both single-ended signals based on logic levels and differential, in particular common-mode-based signals, to continually transmit a serialized signal in an error-free, stable manner.
摘要翻译：本发明涉及一种使用基于逻辑电平和差分（特别是基于共模的信号）的单端信号来连续发送无错误的串行化信号的电路装置（A）和相应的方法，稳定的方式。

124. 发明公开

EP2296279A2 Clock data recovery with selectable phase control 审中-公开
标题翻译：时钟恢复电路用可选择的相位控制
公开(公告)号：EP2296279A2
公开(公告)日：2011-03-16
申请号：EP10172886.3
申请日：2002-08-23
申请人： Rambus Inc.
发明人： Chang, Kun-Yung K. , Wei, Jason C. , Perino, Donald V.
IPC分类号： H03L7/085 , H04L7/02
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0814 , H03L7/089 , H03L7/091 , H04L7/0004 , H04L7/0337 , H04L7/10
摘要： A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit; a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase relationship between the input signal and a first clock signal. The select circuit is coupled to receive the first control signal from the control circuit and coupled to receive a second control signal. The select circuit is responsive to a select signal to select either the first control signal or the second control signal to be output as a selected control signal. The phase adjust circuit is coupled to receive the selected control signal from the select circuit, the phase adjust circuit being responsive to the selected control signal to adjust the phase of the first clock signal.

125. 发明公开

EP2137873A2 DISPOSITIF D'EXTRACTION D'HORLOGE A ASSERVISSEMENT NUMERIQUE DE PHASE SANS REGLAGE EXTERNE 失效
标题翻译： DEVICE FOR时钟信号的无外控制数字控制阶段的回收
公开(公告)号：EP2137873A2
公开(公告)日：2009-12-30
申请号：EP08787918.5
申请日：2008-04-04
申请人： Centre National d'Etudes Spatiales ( C.N.E.S.)
发明人： PIGNOL, Michel , NEVEU, Claude , DEVAL, Yann , BEGUERET, Jean-Baptiste , MAZOUFFRE, Olivier
IPC分类号： H04L7/027 , H04L7/033 , H03L7/24
CPC分类号： H03L7/083 , H03L7/089 , H03L7/091 , H04L7/0004 , H04L7/0276 , H04L7/0331
摘要： The invention relates to a device for extracting a clock signal from a baseband serial signal, consisting of: an injection-locked oscillator (19), and a phase-lock loop (25) including a digital phase detector (26). The oscillator (19) includes a digital input (24) for controlling the value of the frequency thereof and the phase-lock loop (25) includes a counting circuit (30, 35) which totals the relative values of the digital signal delivered by the digital phase detector (26) and delivers a digital control signal for the oscillator (19).

126. 发明公开

EP1895395A9 Information processing apparatus and control method therefor 有权
标题翻译：信息处理装置及其控制方法
公开(公告)号：EP1895395A9
公开(公告)日：2008-07-09
申请号：EP07106271.5
申请日：2007-04-16
申请人： FUJITSU LIMITED
发明人： Osano, Hidekazu c/o FUJITSU LIMITED , Nakayama, Hiroshi c/o FUJITSU LIMITED
IPC分类号： H04L7/00
CPC分类号： G06F3/067 , G06F3/0605 , G06F11/2056 , G06F11/3485 , H04L7/0004
摘要： A mutual electrically connecting part mutually connects a plurality of information processing parts, wherein the mutual connecting part comprises a phase adjusting part configured to adjust a phase from each of the respective ones of the plurality of information processing parts; and the mutual connecting part further has a power supply cut signal transmitting part transmitting a power supply cut signal, indicating that power supply to any one of the plurality of information processing parts is cut, to the phase adjusting part corresponding to the information processing part; and an initializing part initializing the phase adjusting part corresponding to the information proceeding part for which power supply is cut, in response to the transmission of the power supply cut signal from the power supply cut signal transmitting part.

127. 发明公开

EP1552641A1 OPTIMUM INTERPOLATOR METHOD AND APPARATUS FOR DIGITAL TIMING ADJUSTMENT 有权
标题翻译：优化INTERPOLATORVERFAHREN和装置数字定时调整
公开(公告)号：EP1552641A1
公开(公告)日：2005-07-13
申请号：EP03770595.1
申请日：2003-09-30
申请人： INTERDIGITAL TECHNOLOGY CORPORATION
发明人： BULTAN, Aykut , GRIECO, Donald, M.
IPC分类号： H04L7/00 , H04L27/06 , H04B1/69 , G06F7/38 , G06F17/17
CPC分类号： H04L7/0029 , H04B1/70756 , H04B1/7077 , H04B1/7117 , H04L7/0004 , H04L25/0202
摘要： A digital timing synchronizer of a receiver is provided for timing synchronization to a transmitter in a wireless communication system, wherein the received signal has a timing error with respect to a reference code. A channel estimator (11) estimates an initial code phase of the received signal. A code generator (13) generates a timing reference code that is adjustable by integer increments. An interpolation feedback circuit (35) is configured for interpolation and correction of the timing error, whereby the interpolation (14) is achieved through an integer code shift, plus a quantized fractional adjustment selected from a look-up table of quantized fractional adjustment values and their associated predetermined interpolator coefficients, from which a time corrected version of the received signal is produced.

128. 发明授权

EP1195922B1 Demodulation method and apparatus in high speed time division multiplexed packet data transmission 有权
标题翻译：用于在电信系统中使用的时分多址解调高速分组数据的方法和装置
公开(公告)号：EP1195922B1
公开(公告)日：2005-01-05
申请号：EP01127489.1
申请日：1999-02-24
申请人： Ericsson Inc.
发明人： Dent, Paul W. , Dutta, Santanu
IPC分类号： H04B7/212 , H04J3/06
CPC分类号： H04B7/2125 , H04J3/0605 , H04L7/0004 , H04L2007/047

129. 发明公开

EP1397879A4 CLOCK RECOVERY CIRCUIT 有权
标题翻译：时钟恢复电路
公开(公告)号：EP1397879A4
公开(公告)日：2004-12-29
申请号：EP02725899
申请日：2002-05-03
申请人： COREOPTICS INC
发明人： DORSCHKY CLAUS , KUPFER THEODOR
IPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/00 , H04L7/033 , H03L7/22 , H04L1/00
CPC分类号： H03L7/07 , H03L7/095 , H03L7/10 , H03L7/107 , H04L7/0004 , H04L7/033
摘要： A clock recovery circuit for use with a high-speed data signal having a low signal to noise ratio is disclosed. The circuit includes a first phase-locked loop circuit (104) operating in a fast acquisition mode for acquiring the clock from a data signal (D), a second phase locked loop circuit (102) for operating in a normal mode to recover the clock signal (Crec) in the digital data signal once the first phase locked loop circuit (104) has acquired the clock from the data signal, and a switch circuit (sw1, sw2, sw3) responsive to switch control signals for switching between the first phase locked loop circuit (104) and the second phase locked loop circuit (102) after the first phase locked loop circuit (104) has acquired the digital data signal.

130. 发明公开

EP1207623A3 Gated clock recovery circuit 有权
标题翻译：时钟恢复电路交换
公开(公告)号：EP1207623A3
公开(公告)日：2004-11-17
申请号：EP01309756.3
申请日：2001-11-20
申请人： Agere Systems Guardian Corporation
发明人： Dunlop, Alfred Earl , Fischer, Wilhelm Carl
IPC分类号： H03L7/07 , H04L7/033
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL1) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP1, to the second PLL (PLL2) to indirectly initially tune the second PLL. The bias voltage, CAP1, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP2, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate. Thereafter, the bias voltage, CAP2, is removed and the second PLL can operate without being controlled by PLL1 so that the second PLL oscillates in phase with the received data. Simultaneously, the received data starts the oscillator in the second PLL so that the second oscillator is in phase with the received data. The second PLL then maintains this phase relationship between the second oscillator and the received data.

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