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121. 发明授权

US5761099A Programmable logic array integrated circuits with enhanced carry routing 失效
标题翻译：可编程逻辑阵列集成电路，具有增强的携带路由
公开(公告)号：US5761099A
公开(公告)日：1998-06-02
申请号：US497213
申请日：1995-06-30
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H03K19/177 , G06F7/50
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LABs are directly connectable to one another to provide a direct carry chain (70a, 70b) between LABs. The carry chain is enhanced by providing a selector (80) that allows a LAB's carry input to selectively be coupled to either the carry output of an adjacent or nearly LAB or to the global interconnect.
摘要翻译：可编程逻辑器件（10）具有多个可编程逻辑元件（LE）（12），它们被分组在多个逻辑阵列块（LAB）中。提供了一种全局互连结构（20,24），用于将LAB与其他LAB相互连接。相邻或附近的LAB可以彼此直接连接，以便在LAB之间提供直接携带链（70a，70b）。通过提供允许LAB的进位输入选择性地耦合到相邻或接近LAB的进位输出或全局互连的选择器（80）来增强进位链。

122. 发明授权

US5649163A Method of programming an asynchronous load storage device using a representation of a clear/preset storage device 失效
标题翻译：使用清除/预设存储设备的表示来编程异步负载存储设备的方法
公开(公告)号：US5649163A
公开(公告)日：1997-07-15
申请号：US319333
申请日：1994-10-06
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5054
摘要： A method and apparatus for converting a storage device having asynchronous clear and asynchronous preset inputs into an equivalent storage device having asynchronous clear and asynchronous load inputs is provided. If the asynchronous clear/asynchronous preset flip-flop is fed by a preset signal but not a clear signal, the equivalent asynchronous clear/asynchronous load flip-flop is implemented by connecting the preset signal to the clear terminal of the asynchronous clear/asynchronous load flip-flop, disabling the load of the asynchronous clear/asynchronous load flip-flop and inverting the input and output signal of the asynchronous clear/asynchronous preset flip-flop. If both a clear and preset signal are fed to the asynchronous clear/asynchronous preset, the preset function can be reduced to (L*D), and the clear input can be reduced to (C+L*D'), then the flip-flop can be implemented by connecting C, L, and D, to the clear, asynchronous load and asynchronous data inputs of the asynchronous clear/asynchronous load flip-flop. If aforementioned conditions are not met, the asynchronous clear/asynchronous preset flip-flop is implemented by placing V.sub.cc on the asynchronous data input and connecting the preset signal of the asynchronous clear/asynchronous preset flip-flop to the asynchronous load input of the asynchronous clear/asynchronous flip-flop.
摘要翻译：提供一种用于将具有异步清除和异步预设输入的存储设备转换成具有异步清除和异步负载输入的等效存储设备的方法和装置。如果异步清除/异步预置触发器由预置信号馈送而不是清除信号，则通过将预置信号连接到异步清除/异步负载的清零端来实现等效的异步清除/异步负载触发器触发器，禁用异步清零/异步负载触发器的负载，并反相异步清零/异步预置触发器的输入和输出信号。如果清除和预设信号都被馈送到异步清除/异步预设，则预设功能可以减少到（L * D），并且清除输入可以减少到（C + L * D'），然后翻转可以通过将C，L和D连接到异步清零/异步负载触发器的清除异步负载和异步数据输入来实现。如果不符合上述条件，则异步清零/异步预置触发器通过将Vcc置于异步数据输入端并将异步清零/异步预置触发器的预置信号连接到异步清零的异步负载输入来实现 /异步触发器。

123. 发明授权

US5557217A High-density erasable programmable logic device architecture using multiplexer interconnections 失效
公开(公告)号：US5557217A
公开(公告)日：1996-09-17
申请号：US331964
申请日：1994-10-31
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.

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