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121. 发明授权

US5554710A Conductive polymers and process for preparing the same 失效
标题翻译：导电聚合物及其制备方法
公开(公告)号：US5554710A
公开(公告)日：1996-09-10
申请号：US197986
申请日：1994-02-17
申请人： Shigeru Mori , Motoo Fukushima , Eiichi Tabei , Yoshitaka Hamada , Seizi Katayama
发明人： Shigeru Mori , Motoo Fukushima , Eiichi Tabei , Yoshitaka Hamada , Seizi Katayama
IPC分类号： C08G77/60 , C08L83/16 , C09D183/16 , H01M6/18 , C08G77/20 , B05D5/12 , H01M4/70
CPC分类号： C09D183/16 , C08G77/60 , C08L83/16 , H01M6/181
摘要： A conductive polymer comprises a silicon-containing polymer having, in the main chain thereof, Si--Si bonds or both Si--Si bonds and C--C multiple bonds, and ferric chloride doped in said polymer through vapor phase doping. A method for preparing such a conductive polymer is also described.
摘要翻译：导电聚合物包括在其主链中具有Si-Si键或Si-Si键和C-C多键的含硅聚合物，以及通过气相掺杂掺杂在所述聚合物中的氯化铁。还描述了制备这种导电聚合物的方法。

122. 发明授权

US5499214A Oscillator circuit generating a clock signal having a temperature dependent cycle and a semiconductor memory device including the same 失效
标题翻译：产生具有温度相关周期的时钟信号的振荡器电路和包括该时钟信号的半导体存储器件
公开(公告)号：US5499214A
公开(公告)日：1996-03-12
申请号：US257845
申请日：1994-06-10
申请人： Shigeru Mori , Takeshi Kajimoto , Masanori Hayashikoshi
发明人： Shigeru Mori , Takeshi Kajimoto , Masanori Hayashikoshi
IPC分类号： G11C11/406 , G11C11/4076 , H03K3/03 , H03K3/354 , G11C7/00
CPC分类号： G11C11/4076 , G11C11/406 , H03K3/0315 , H03K3/354
摘要： In a semiconductor memory device, a constant voltage is applied to a resistor having a positive temperature coefficient, whereby a first reference current flowing through that resistor is converted into a voltage by a resistor. That voltage is converted into a second reference current by a P channel MOS transistor, whereby a second current of a value equal to the value of the second reference current flows through each of a plurality of inverters by a current mirror circuit. These inverters are connected in a ring manner to form a ring oscillator. The first reference current becomes lower as the operating temperature rises, whereby the second reference current increases. As a result, the oscillator cycle of the ring oscillator becomes shorter as the operating temperature rises.
摘要翻译：在半导体存储器件中，将恒定电压施加到具有正温度系数的电阻器，由此流过该电阻器的第一参考电流被电阻器转换成电压。该电压通过P沟道MOS晶体管转换为第二基准电流，由此通过电流镜电路使等于第二基准电流的值的第二电流流过多个反相器中的每一个。这些反相器以环形方式连接以形成环形振荡器。随着工作温度升高，第一参考电流变低，从而第二参考电流增加。结果，环路振荡器的振荡器周期随着工作温度升高而变短。

123. 发明授权

US5442277A Internal power supply circuit for generating internal power supply potential by lowering external power supply potential 失效
标题翻译：内部电源电路，通过降低外部电源电位产生内部电源电位
公开(公告)号：US5442277A
公开(公告)日：1995-08-15
申请号：US196730
申请日：1994-02-15
申请人： Shigeru Mori , Takeshi Kajimoto
发明人： Shigeru Mori , Takeshi Kajimoto
IPC分类号： G05F1/56 , G05F1/46 , G11C11/407 , G11C11/413 , H02J1/00 , G05F3/04
CPC分类号： G05F1/465
摘要： An internal power supply circuit includes a main internal power supply potential generating circuit for generating an internal power supply potential based on a prescribed reference potential, and an auxiliary internal power supply potential generating circuit which is activated in response to a control signal and when activated, generating an internal power supply potential together with the main internal power supply potential generating circuit. The auxiliary internal power supply potential generating circuit includes a P channel MOS transistor for driving, a differential amplifying circuit for controlling the driving transistor by comparing the internal power supply potential with the reference potential and a standby potential supplying circuit for applying a standby potential which is slightly higher than the threshold potential at the which the transistor is rendered conductive, to the gate of the driving transistor while the differential amplifying circuit is not activated. In the internal power supply circuit, since a standby potential which is slightly higher than the threshold potential is applied to the gate of the driving transistor at the standby state, charges are immediately supplied to an output node when the auxiliary internal power supply potential generating circuit is activated.
摘要翻译：内部电源电路包括：用于产生基于规定参考电位的内部电源电位的主内部电源电位产生电路;以及响应于控制信号而被激活的辅助内部电源电位产生电路，与主内部电源电位产生电路一起产生内部电源电位。辅助内部电源电位产生电路包括用于驱动的P沟道MOS晶体管，用于通过将内部电源电位与参考电位进行比较来控制驱动晶体管的差分放大电路和用于施加待机电位的备用电位供应电路，略高于晶体管导通的阈值电位，而差分放大电路未被激活时，驱动晶体管的栅极。在内部电源电路中，由于在待机状态下将稍微高于阈值电位的待机电位施加到驱动晶体管的栅极，因此当辅助内部电源电位产生电路被激活。

124. 发明授权

US5436911A Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
标题翻译：半导体存储器件，包括测试电路及其操作方法
公开(公告)号：US5436911A
公开(公告)日：1995-07-25
申请号：US307082
申请日：1994-09-16
申请人： Shigeru Mori
发明人： Shigeru Mori
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/34 , G11C7/00
CPC分类号： G11C29/34
摘要： A semiconductor memory device comprises a memory array. Each bit line pairs connected to a first amplifier. Write buses, read buses and a read/test circuit are provided. A column decoder selects simultaneously every other plurality of bit line pair at the time of testing. The read/test circuit compares the data read out from the selected plurality of bit line pair with the given expected data to provide the comparison result. Then the column decoder selects simultaneously the remaining one other plurality of bit line pairs. The read/test circuit compares data read out from the selected plurality of bit line pair with a given expected data to provide the comparison result.
摘要翻译：半导体存储器件包括存储器阵列。每个位线对连接到第一放大器。提供写总线，读总线和读/测电路。列解码器在测试时同时选择其他多个位线对。读/测试电路将从所选择的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。然后，列解码器同时选择剩余的另一个多个位线对。读取/测试电路将从所选择的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

125. 发明授权

US5374758A Hydro-terminated polysilane and process for making 失效
标题翻译：水解端基聚硅烷和制备方法
公开(公告)号：US5374758A
公开(公告)日：1994-12-20
申请号：US96259
申请日：1993-07-26
申请人： Shigeru Mori , Eiichi Tabei
发明人： Shigeru Mori , Eiichi Tabei
IPC分类号： C07F7/08 , C08G77/48 , C08G77/60
CPC分类号： C07F7/0896
摘要： A both end hydro-terminated polysilane is of the formula: H[(R.sup.1 R.sup.2 Si).sub.n (R.sup.3 R.sup.4 Si).sub.m ].sub.k H wherein R.sup.1, R.sup.2, R.sup.3 and R.sup.4 are independently C.sub.1 -C.sub.12 alkyl groups or aryl groups and letters n, m and k are numbers in the range: 0.ltoreq.n.ltoreq.10, 0.ltoreq.m.ltoreq.10, n+m.gtoreq.10, and k.gtoreq.1. It is prepared by dissolving a corresponding chloro-terminated polysilane in a solvent and reducing with LiAlH.sub.4 in an inert gas atmosphere.
摘要翻译：两末端加氢封端的聚硅烷具有下式：H [（R 1 R 2 Si）n（R 3 R 4 Si）m] k H其中R 1，R 2，R 3和R 4独立地为C 1 -C 12烷基或芳基，并且字母n，m和k为范围内的数字：0 / = 10，k> / = 1。通过将相应的氯封端的聚硅烷溶解在溶剂中并在惰性气体气氛中用LiAlH 4还原制备。

126. 发明授权

US5369354A Intermediate voltage generating circuit having low output impedance 失效
标题翻译：中压产生电路具有低输出阻抗
公开(公告)号：US5369354A
公开(公告)日：1994-11-29
申请号：US107882
申请日：1993-08-18
申请人： Shigeru Mori
发明人： Shigeru Mori
IPC分类号： G05F1/618 , G05F3/24 , G11C11/407 , G05F3/16 , G05F3/20
CPC分类号： G05F3/24
摘要： By reducing output impedance of an intermediate voltage generating circuit used in a DRAM and the like, an output voltage quickly recovers to an intermediate voltage even in the case where the output voltage fluctuates heavily. The intermediate voltage generating circuit includes a first reference voltage generating circuit, a second reference voltage generating circuit, a first intermediate voltage output stage, and a second intermediate voltage output stage. An MOS transistor configuring a current mirror is provided with the first and second intermediate voltage output stages. The size of the MOS transistor of the second intermediate voltage output stage is larger than that of a transistor of the first intermediate voltage output stage. As a result, in response to a current flowing in either transistor of the first intermediate voltage output stage, a current having a value equal to or more than that of the current flowing in either transistor of the first intermediate voltage output stage is supplied to an output node, whereby the output impedance is reduced.
摘要翻译：通过减少在DRAM等中使用的中间电压产生电路的输出阻抗，即使在输出电压剧烈波动的情况下，输出电压也迅速恢复到中间电压。中间电压产生电路包括第一参考电压产生电路，第二参考电压产生电路，第一中间电压输出级和第二中间电压输出级。配置电流镜的MOS晶体管具有第一和第二中间电压输出级。第二中间电压输出级的MOS晶体管的尺寸大于第一中间电压输出级的晶体管的尺寸。结果，响应于在第一中间电压输出级的任一晶体管中流动的电流，具有等于或大于在第一中间电压输出级的任一晶体管中流动的电流的电流的电流被提供给输出节点，从而减小输出阻抗。

127. 发明授权

US5359106A Terminally reactive polysilane and process for making 失效
标题翻译：端反应性聚硅烷和制备方法
公开(公告)号：US5359106A
公开(公告)日：1994-10-25
申请号：US171437
申请日：1993-12-22
申请人： Eiichi Tabei , Shigeru Mori
发明人： Eiichi Tabei , Shigeru Mori
IPC分类号： C07F7/08 , C07F7/18 , C08G77/48 , C08G77/60 , C07F7/10
CPC分类号： C08G77/60 , C07F7/0818 , C07F7/1836
摘要： Terminally reactive polysilanes of formula (1) are novel. ##STR1## R.sup.1, R.sup.2, R.sup.3, and R.sup.4 are independently C.sub.1-12 alkyl or aryl groups, R.sup.5 is an organic group containing an alkoxysilyl, epoxy, glycidyloxy, acryl, methacryl, acetoxysilyl or amino group, A is a C.sub.2-6 alkylene group, n, m and k are numbers in the range: 0.ltoreq.n.ltoreq.10, 0.ltoreq.m.ltoreq.10, n+m.gtoreq.10, and k.gtoreq.1. The polysilanes are prepared by effecting addition reaction between a hydro-terminated polysilane and an unsaturated group-containing reactive compound in the presence of a hydrosilylation catalyst.
摘要翻译：式（1）的末端反应性聚硅烷是新颖的。（1）R1，R2，R3和R4分别是C1-12烷基或芳基，R5是含有烷氧基甲硅烷基，环氧基，缩水甘油氧基，丙烯酰基，甲基丙烯酰基，乙酰氧基甲硅烷基或氨基的有机基团，A是C2 -6亚烷基，n，m和k是以下范围内的数字：0≤n≤10,0≤m≤10，n + m> = 10，k> / = 1 。聚硅烷通过在氢化硅烷化催化剂的存在下进行加氢封端的聚硅烷和含不饱和基团的反应性化合物之间的加成反应来制备。

128. 发明授权

US5336798A Preparation of polysilane oligomers 失效
标题翻译：聚硅烷低聚物的制备
公开(公告)号：US5336798A
公开(公告)日：1994-08-09
申请号：US32109
申请日：1993-03-17
申请人： Motoo Fukushima , Shigeru Mori
发明人： Motoo Fukushima , Shigeru Mori
IPC分类号： C07F7/08 , C08G77/60
CPC分类号： C08G77/60 , C07F7/0896
摘要： There is disclosed a method for preparing a polysilane oligomer having a terminal SiH group represented by the structural formula (1): ##STR1## wherein R.sup.1 to R.sup.4 are monovalent hydrocarbon groups with proviso that at least one of R.sup.1 to R.sup.4 is an aryl group, n and m are integers of 1 or more, and n+m is equal to 3, 4, 5 or 6 comprising the step of reacting a disilane of the structural formula (2): ##STR2## wherein R.sup.1 to R.sup.4 are as defined above in the presence of a Group VIII transition metal complex catalyst.
摘要翻译：公开了一种制备具有由结构式（1）表示的末端SiH基团的聚硅烷低聚物的方法：其中R 1至R 4为单价烃基，条件是R 1至R 4中的至少一个为芳基，n和m是1以上的整数，n + m等于3,4,5或6，包括使结构式（2）的乙硅烷反应的步骤：其中R1 至R 4如上述在VIII族过渡金属络合物催化剂存在下所定义。

129. 发明授权

US5233068A Organic silicon compounds and method for making 失效
标题翻译：有机硅化合物及其制备方法
公开(公告)号：US5233068A
公开(公告)日：1993-08-03
申请号：US978543
申请日：1992-11-19
申请人： Motoo Fukushima , Shigeru Mori
发明人： Motoo Fukushima , Shigeru Mori
IPC分类号： C07F7/08 , C07F7/21
CPC分类号： C07F7/0841 , C07F7/21
摘要： Novel cyclic organic silicon compounds of formula (1) can be synthesized in high yields and high purity by reacting a dichlorosilane of formula (3) with a cyclotrisiloxane of formula (4) in an aprotic polar solvent to form an .alpha.,.omega.-dichlorosiloxane of formula (2), and reacting the .alpha.,.omega.-dichlorosiloxane with an alkali metal according to the following reaction scheme. ##STR1##
摘要翻译：式（1）的新型环状有机硅化合物可以通过在非质子传递极性溶剂中使式（3）的二氯硅烷与式（4）的环三硅氧烷反应，以高产率和高纯度合成，形成α，ω-二氯硅氧烷式（2）的化合物，并使α，ω-二氯硅氧烷与碱金属反应。 + TR

130. 发明授权

US5159043A Preparation of polyorganosilanes 失效
标题翻译：聚有机硅烷的制备
公开(公告)号：US5159043A
公开(公告)日：1992-10-27
申请号：US812279
申请日：1991-12-23
申请人： Shigeru Mori , Eiichi Tabei , Motoo Fukushima , Yoshinori Hida
发明人： Shigeru Mori , Eiichi Tabei , Motoo Fukushima , Yoshinori Hida
IPC分类号： C08G77/48 , C08G77/60
CPC分类号： C08G77/60
摘要： Polyorganosilanes are prepared through contact reaction of an organodihalosilane with alkali metal fine particles dispersed in an organic solvent. the reaction solution is adjusted to an acidity of pH 3 to 7 before or after the step of deactivating the excess alkali metal in the reaction solution. The alkali metal halide is removed from the reaction solution by dissolving it in water. Formation of insoluble components is minimized.
摘要翻译：聚有机硅烷通过有机二卤硅烷与分散在有机溶剂中的碱金属微粒的接触反应制备。在使反应溶液中过量的碱金属失活的步骤之前或之后将反应溶液调节至pH 3至7的酸度。将碱金属卤化物溶解在水中从反应溶液中除去。不溶性组分的形成最小化。

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