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121. 发明授权

US06865695B2 Robust system bus recovery 有权
标题翻译：强大的系统总线恢复
公开(公告)号：US06865695B2
公开(公告)日：2005-03-08
申请号：US09915668
申请日：2001-07-26
申请人： Jody Bern Joyner , Ravi Kumar Arimilli , Jerry Don Lewis , Vicente Enrique Chung
发明人： Jody Bern Joyner , Ravi Kumar Arimilli , Jerry Don Lewis , Vicente Enrique Chung
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： G06F11/2007
摘要： A computer system of a number of processing nodes operate either in a loop configuration or off of a common bus with high speed, high performance wide bandwidth characteristics. The processing nodes in the system are also interconnected by a separate narrow bandwidth, low frequency recovery bus. When problems arise with node operations on the high speed bus, operations are transferred to the low frequency recovery bus and continue there at a slower rate for recovery operations. The recovery technique may be used to increase system speed and performance on a dynamic basis.
摘要翻译：多个处理节点的计算机系统以具有高速，高性能宽带宽特性的公共总线的环路配置或关闭操作。系统中的处理节点也通过单独的窄带宽，低频恢复总线互连。当高速总线上的节点操作出现问题时，操作将传输到低频恢复总线，并以较慢的速率继续进行恢复操作。恢复技术可以用于在动态基础上提高系统速度和性能。

122. 发明授权

US06823471B1 Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem 失效
标题翻译：一种通过可重配置散列存储子系统在数据处理系统内提供高可用性的方法
公开(公告)号：US06823471B1
公开(公告)日：2004-11-23
申请号：US09364281
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1100
CPC分类号： G06F11/20
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
摘要翻译：处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。执行资源，数据存储和指令排序单元中的至少一个由具有用于处理多个数据流中的相应一个的类似功能的多个硬件分区来实现。如果在特定硬件分区中检测到错误，则分配给该硬件分区的数据流被重新分配给多个硬件分区中的另一个，从而防止其中一个硬件分区中的错误导致灾难性故障。

123. 发明授权

US06519649B1 Multi-node data processing system and communication protocol having a partial combined response 失效
标题翻译：多节点数据处理系统和具有部分组合响应的通信协议
公开(公告)号：US06519649B1
公开(公告)日：2003-02-11
申请号：US09436899
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F12/0813
摘要： A data processing system includes an interconnect and first and second nodes, coupled to the interconnect, that each include at least one agent. Each agent within the first and second nodes outputs a snoop response in response to snooping a transaction on the interconnect. Utilizing the snoop response of each agent within the first node, first response logic within the first node produces a first cumulative combined response. This first cumulative combined response is then combined by second response logic in the second node with the snoop response of each agent in the second node to produce a second cumulative combined response. After a complete combined response is obtained in this manner, the complete combined response is distributed to all nodes so that each agent can determine its response, if any, to the transaction.
摘要翻译：数据处理系统包括互连以及耦合到互连的第一和第二节点，每个包括至少一个代理。第一和第二节点内的每个代理响应于窥探互连上的事务而输出一个窥探响应。利用第一节点内的每个代理的窥探响应，第一节点内的第一响应逻辑产生第一累积组合响应。然后，该第一累积组合响应由第二节点中的第二响应逻辑与第二节点中每个代理的窥探响应组合以产生第二累积组合响应。在以这种方式获得完整的组合响应之后，完整的组合响应被分配给所有节点，使得每个代理可以确定其对事务的响应（如果有的话）。

124. 发明授权

US06446165B1 Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) 失效
标题翻译：具有HSA（散列存储架构）的数据处理系统中的依赖于地址的缓存行为
公开(公告)号：US06446165B1
公开(公告)日：2002-09-03
申请号：US09364287
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0811
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
摘要翻译：处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。存储由执行单元使用的数据的高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据，并且实现多种缓存行为。不同的缓存行为可以包括不同的内存更新策略，不同的一致性协议，不同的预取行为以及不同的缓存行替换策略。

125. 发明授权

US5958011A System utilizing mastering and snooping circuitry that operate in response to clock signals having different frequencies generated by the communication controller 失效
标题翻译：利用由通信控制器产生的具有不同频率的时钟信号而工作的母带和窥探电路的系统
公开(公告)号：US5958011A
公开(公告)日：1999-09-28
申请号：US829579
申请日：1997-03-31
申请人： Ravi Kumar Arimilli , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Jerry Don Lewis
IPC分类号： G06F11/30 , G06F13/14
CPC分类号： G06F13/423
摘要： A data processing system and method of communicating data in a data processing system are described. The data processing system includes a communication network to which a plurality of devices are coupled. At least one device among the plurality of devices coupled to the communication network includes mastering circuitry and snooping circuitry. According to the method, a first timing signal having a first frequency and a second timing signal having a second frequency different from the first frequency are generated. Communication transactions on the communication network are initiated utilizing the mastering circuitry, which operates in response to the first timing signal, and are monitored utilizing the snooping circuitry, which operates in response to the second timing signal.
摘要翻译：描述了在数据处理系统中传送数据的数据处理系统和方法。数据处理系统包括多个设备耦合到的通信网络。耦合到通信网络的多个设备中的至少一个设备包括母盘制作电路和窥探电路。根据该方法，产生具有第一频率的第一定时信号和具有与第一频率不同的第二频率的第二定时信号。在通信网络上的通信交易是利用主控电路来启动的，该母盘控制电路响应于第一定时信号进行操作，并且利用响应于第二定时信号而工作的监听电路进行监视。

126. 发明授权

US07526631B2 Data processing system with backplane and processor books configurable to support both technical and commercial workloads 失效
标题翻译：具有背板和处理器书籍的数据处理系统可配置为支持技术和商业工作负载
公开(公告)号：US07526631B2
公开(公告)日：2009-04-28
申请号：US10425421
申请日：2003-04-28
申请人： Ravi Kumar Arimilli , Vicente Enrique Chung , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Vicente Enrique Chung , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8007
摘要： A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.
摘要翻译：基于重新配置外部接线互连的动态或静态机制，处理器书旨在支持商业工作负载和技术工作负载。处理器书被配置为具有外部连接器总线（ECB）的商业工作负载处理系统的构建块。处理器手册还提供了路由逻辑，以使ECB能够用于同一处理器书中的书本到书籍路由或路由。提供了一种表格特定的布线方案，用于将一个MCM的芯片上运行的ECB与处理器簿上的第二个MCM的芯片耦合，使得第一个MCM的芯片直接连接到逻辑上的第二个MCM的芯片最远的地方，反之亦然。一旦根据布线方案完成了ECB的接线，则其操作和功能特征反映了为技术工作负载配置的处理器书。

127. 发明申请

US20080209163A1 DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURABLE TO SUPPPRT BOTH TECHNICAL AND COMMERCIAL WORKLOADS 审中-公开
标题翻译：具有背板和处理器书的数据处理系统可配置以支持两种技术和商业工作
公开(公告)号：US20080209163A1
公开(公告)日：2008-08-28
申请号：US12118199
申请日：2008-05-09
申请人： Ravi Kumar Arimilli , Vicente Enrique Chung , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Vicente Enrique Chung , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F15/76
CPC分类号： G06F15/8007
摘要： A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.
摘要翻译：基于重新配置外部接线互连的动态或静态机制，处理器书旨在支持商业工作负载和技术工作负载。处理器书被配置为具有外部连接器总线（ECB）的商业工作负载处理系统的构建块。处理器手册还提供了路由逻辑，以使ECB能够用于同一处理器书中的书本到书籍路由或路由。提供了一种表格特定的布线方案，用于将一个MCM的芯片上运行的ECB与处理器簿上的第二个MCM的芯片耦合，使得第一个MCM的芯片直接连接到逻辑上的第二个MCM的芯片最远的地方，反之亦然。一旦根据布线方案完成了ECB的接线，则其操作和功能特征反映了为技术工作负载配置的处理器书。

128. 发明授权

US07007128B2 Multiprocessor data processing system having a data routing mechanism regulated through control communication 失效
标题翻译：具有通过控制通信调节的数据路由机制的多处理器数据处理系统
公开(公告)号：US07007128B2
公开(公告)日：2006-02-28
申请号：US10752835
申请日：2004-01-07
申请人： Ravi Kumar Arimilli , Jerry Don Lewis , Vicente Enrique Chung , Jody Bern Joyner
发明人： Ravi Kumar Arimilli , Jerry Don Lewis , Vicente Enrique Chung , Jody Bern Joyner
IPC分类号： G06F13/00
CPC分类号： G06F13/4027
摘要： A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units. The first processing unit requests approval from the third processing unit via the control channel to transmit a data communication to the second processing unit, and the third processing unit approves or delays transmission of the data communication in a response transmitted via the control channel.
摘要翻译：数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。在一个实现中，数据处理系统至少包括第一到第三处理单元，耦合到多个处理单元的数据存储器和互连结构。所述互连结构至少包括将所述第一处理单元耦合到所述第二处理单元的第一数据总线和将所述第三处理单元耦合到所述第二处理单元的第二数据总线，使得所述第一处理单元和所述第三处理单元可以向第二处理单元处理单元。数据处理系统还包括耦合第一和第三处理单元的控制通道。第一处理单元经由控制信道从第三处理单元请求批准，以将数据通信发送到第二处理单元，并且第三处理单元在经由控制信道发送的响应中批准或延迟数据通信的传输。

129. 发明授权

US06910062B2 Method and apparatus for transmitting packets within a symmetric multiprocessor system 失效
标题翻译：用于在对称多处理器系统内传输分组的方法和装置
公开(公告)号：US06910062B2
公开(公告)日：2005-06-21
申请号：US09918812
申请日：2001-07-31
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： H04L12/42 , G06F15/17 , G06F15/16
CPC分类号： G06F15/17
摘要： The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.
摘要翻译：对称多处理器系统包括多个处理节点，每个节点具有多个代理，通过互连彼此连接。请求事务由主节点中的主代理发起到所有接收节点。生成用于与请求事务相关联的写计数器号。主代理然后等待来自接收节点的组合响应。在接收到组合响应之后，根据组合的响应，将数据分组从主代理发送到所有预期的接收节点。在发送数据分组之后，主节点中的主代理准备好发送另一请求事务以及新的写计数器号，而不需要等待来自接收节点的确认。

130. 发明授权

US06671712B1 Multi-node data processing system having a non-hierarchical interconnect architecture 有权
标题翻译：具有非分层互连架构的多节点数据处理系统
公开(公告)号：US06671712B1
公开(公告)日：2003-12-30
申请号：US09436898
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F13/4217
摘要： A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency. The non-hierarchical interconnect architecture also permits design flexibility in that the segment of the interconnect within each node can be independently implemented by a set of buses or as a switch, depending upon cost and performance considerations.
摘要翻译：数据处理系统包括多个节点，每个节点包含至少一个代理，以及节点内的代理可访问的数据存储。多个节点通过包括多个非阻塞单向地址信道和至少一个单向数据信道的非分层互连来耦合。在所有多个地址信道上分别耦合到并且窥探事务的代理只能在相关联的地址信道上发布事务。当前的非分层互连架构采用的单向信道允许高频抽运操作对于传统的双向共享系统总线是不可能的。另外，与传统分层系统相比，由于没有层间（例如，总线采集）通信延迟，与本地高速缓存未命中所产生的远程（高速缓存或主）存储器的访问延迟大大降低。非分层互连架构还允许设计灵活性，因为根据成本和性能考虑，每个节点内的互连部分可以由一组总线或开关单独地实现。

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