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121. 发明授权

US06534403B2 Method of making a contact and via structure 有权
标题翻译：制造接触和通孔结构的方法
公开(公告)号：US06534403B2
公开(公告)日：2003-03-18
申请号：US09939321
申请日：2001-08-24
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： H01L2144
CPC分类号： H01L21/76804 , H01L21/76895 , H01L23/5226 , H01L23/5252 , H01L28/00 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and a second sidewall wherein the first sidewall is opposite the second sidewall. The first sidewall has a stair step configuration such that the first sidewall is closer to the second sidewall at the bottom of the opening than at the top of the opening. A conductive film is then formed on the first sidewall in the opening and on the bottom of the opening on the conductive film.
摘要翻译：本发明是一种接触/通孔，其包括及其制造方法。本发明的接触/通孔包括导电膜。在导电膜上形成具有顶部和底部的开口。开口具有第一侧壁和第二侧壁，其中第一侧壁与第二侧壁相对。第一侧壁具有楼梯台阶构造，使得第一侧壁在开口底部处比开口顶部更靠近第二侧壁。然后在导电膜上的开口的开口和底部的第一侧壁上形成导电膜。

122. 发明授权

US6091129A Self-aligned trench isolated structure 失效
标题翻译：自对准沟隔离结构
公开(公告)号：US6091129A
公开(公告)日：2000-07-18
申请号：US666754
申请日：1996-06-19
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： H01L21/28 , H01L21/60 , H01L21/762 , H01L21/763 , H01L21/768 , H01L21/04 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28123 , H01L21/76235 , H01L21/763 , H01L21/76804 , H01L21/76831 , H01L21/76841 , H01L21/76895 , H01L21/76897
摘要： A trench-isolated active device and a method of forming a trench-isolated active device on a semiconductor substrate wherein the conductive layer of the device is self-aligned with an isolation trench is disclosed. The method includes applying a conductive layer over a dielectric layer (e.g., gate oxide), forming an opening in the conductive layer and the dielectric layer, forming a trench in the substrate corresponding to the opening, passivating the side walls of the trench with a dielectric material, and filling the trench with a dielectric material. The structure includes a semiconductor substrate having a trench defining a cell region, conductive material in the cell region and adjacent to the trench, and a layer of dielectric material on the side walls of the trench and on the conductive material adjacent to the trench. The invention further contemplates that the trench contains dielectric material, preferably soft glass. The conductive material layer is self-aligned to the isolation trench, so there is no overlap of the conductive material and the isolation trench, and the isolation trench may be a minimum width necessary to isolate the device.
摘要翻译：公开了沟槽隔离有源器件和在半导体衬底上形成沟槽隔离有源器件的方法，其中器件的导电层与隔离沟槽自对准。该方法包括在电介质层（例如，栅极氧化物）上施加导电层，在导电层和电介质层中形成开口，在对应于开口的衬底中形成沟槽，用沟槽的侧壁钝化沟槽电介质材料，并用电介质材料填充沟槽。该结构包括半导体衬底，其具有限定单元区域的沟槽，单元区域中的导电材料并且与沟槽相邻，以及在沟槽的侧壁上以及邻近沟槽的导电材料上的介电材料层。本发明还考虑到沟槽包含电介质材料，优选软玻璃。导电材料层与隔离沟槽自对准，因此导电材料和隔离沟槽不重叠，隔离沟槽可以是隔离器件所需的最小宽度。

123. 发明授权

US6016012A Thin liner layer providing reduced via resistance 失效
标题翻译：薄衬层提供降低的通孔电阻
公开(公告)号：US6016012A
公开(公告)日：2000-01-18
申请号：US744248
申请日：1996-11-05
申请人： Ahmad Chatila , Kuantai Yeh , James M. Cleeves , Daniel Arnzen , Roger Caldwell
发明人： Ahmad Chatila , Kuantai Yeh , James M. Cleeves , Daniel Arnzen , Roger Caldwell
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L29/43
CPC分类号： H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53257 , H01L2924/0002
摘要： The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.
摘要翻译：本发明涉及包含通孔的半导体器件和在半导体器件中形成通孔的方法。

124. 发明授权

US5710061A Disposable post processing for semiconductor device fabrication 失效
标题翻译：半导体器件制造的一次性后处理
公开(公告)号：US5710061A
公开(公告)日：1998-01-20
申请号：US515675
申请日：1995-08-17
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/283
CPC分类号： H01L21/76897
摘要： A disposable post process allows openings to be created in a layer formed over a semiconductor wafer, for example to create self-aligned contacts. A layer of material is formed over a semiconductor wafer and subsequently patterned into posts which define the location and shape of openings to be formed in a subsequently formed planar layer. After the planar layer is formed to surround the posts, the posts are removed to create openings in the planar layer. These openings may then be used to form suitable contacts.
摘要翻译：一次性后处理允许在形成在半导体晶片上的层中产生开口，例如以产生自对准接触。在半导体晶片上形成一层材料，随后将其图案化成柱，其限定待形成在随后形成的平面层中的开口的位置和形状。在形成平面层以围绕柱之后，移除柱以在平面层中形成开口。然后可以使用这些开口形成合适的触点。

125. 发明授权

US5686223A Method for reduced pitch lithography 失效
公开(公告)号：US5686223A
公开(公告)日：1997-11-11
申请号：US740014
申请日：1996-10-23
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： G03F7/00 , G03F7/20
CPC分类号： G03F7/70466 , G03F7/0035 , G03F7/2022
摘要： A lithographic patterning process uses multiple exposures to provide for relatively reduced pitch for features of a single patterned layer. A first imaging layer is exposed to radiation in accordance with a first pattern and developed. The resulting patterned layer is stabilized. A second imaging layer is subsequently formed to surround the first patterned layer, exposed to radiation in accordance with a second pattern, and developed to form a second patterned layer. As the first patterned layer has been stabilized, the first patterned layer remains with the second patterned layer to produce a single patterned layer. For another embodiment, a single imaging layer is patterned by exposure to radiation in accordance with two separate patterns. An exposed portion of the imaging layer is suitably stabilized to withstand subsequent lithographic process steps.

126. 发明授权

US5652182A Disposable posts for self-aligned non-enclosed contacts 失效
标题翻译：用于自对准非封闭式触点的一次性支柱
公开(公告)号：US5652182A
公开(公告)日：1997-07-29
申请号：US581061
申请日：1995-12-29
申请人： James M. Cleeves
发明人： James M. Cleeves
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76895 , H01L21/76802
摘要： A disposable post process for contact openings to interconnect material of reduced geometry and no enlarged landing pads is disclosed. A layer of material is formed over interconnect regions on a semiconductor wafer and subsequently patterned into posts which define the location and shape of openings to be formed in a subsequently formed planar layer. After a layer is formed to surround the posts, the posts are removed to create openings in the layer above underlying interconnect regions. These openings may then be used to form suitable contacts to the interconnect regions.
摘要翻译：公开了一种用于接合开口以互连减小的几何形状的材料并且没有扩大的着陆垫的一次性后处理。在半导体晶片上的互连区域上形成一层材料，随后将其图案化为限定待形成的平面层形成的开口的位置和形状的柱。在形成层以围绕柱之后，移除柱以在下面的互连区域上方的层中形成开口。然后可以使用这些开口来形成到互连区域的合适的触点。

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