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121. 发明授权

US09159568B2 Method for fabricating memory cells having split charge storage nodes 有权
标题翻译：用于制造具有分离电荷存储节点的存储单元的方法
公开(公告)号：US09159568B2
公开(公告)日：2015-10-13
申请号：US11639666
申请日：2006-12-15
申请人： Chungho Lee , Wei Zheng , Chi Chang , Unsoon Kim , Hiroyuki Kinoshita
发明人： Chungho Lee , Wei Zheng , Chi Chang , Unsoon Kim , Hiroyuki Kinoshita
IPC分类号： H01L21/28 , H01L29/66 , H01L29/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/1037 , H01L29/1083 , H01L29/42332 , H01L29/42348 , H01L29/66537 , H01L29/7887 , H01L29/7923
摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.
摘要翻译：公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件第二元件的侧壁。形成与第一存储元件和第二存储元件接触的字线。

122. 发明授权

US08564042B2 Dual storage node memory 有权
标题翻译：双存储节点存储器
公开(公告)号：US08564042B2
公开(公告)日：2013-10-22
申请号：US11702845
申请日：2007-02-05
申请人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
发明人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
IPC分类号： H01L29/94
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括第一电荷存储元件和第二电荷存储元件，其中第一和第二电荷存储元件包括氮化物。存储单元还包括形成在第一和第二电荷存储元件之间的绝缘层。绝缘层提供第一和第二电荷存储元件之间的绝缘。

123. 发明申请

US20120307988A1 COMPUTER SYSTEM AND PROCESSOR HAVING INTEGRATED PHONE FUNCTIONALITY 有权
标题翻译：具有集成电话功能的计算机系统和处理器
公开(公告)号：US20120307988A1
公开(公告)日：2012-12-06
申请号：US13584527
申请日：2012-08-13
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： H04M11/00
CPC分类号： H04M1/2473 , G06F3/021 , G06F3/023 , G06F3/0489
摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.
摘要翻译：包括电话功能的计算机系统。计算机系统包括第一键盘和第一显示器。计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。计算机系统可以在第一模式，第二模式或第三模式中操作。在第一模式中，只有电话部分被激活，并且电话部分提供放置和接收电话呼叫的功能，而不从计算机系统移除。在第二模式中，处理器的电话部分和第一功能单元被激活。在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

124. 发明授权

US07844805B2 Portable processing device having a modem selectively coupled to a RISC core or a CISC core 有权
标题翻译：具有调制解调器的便携式处理设备选择性地耦合到RISC核心或CISC核心
公开(公告)号：US07844805B2
公开(公告)日：2010-11-30
申请号：US11758772
申请日：2007-06-06
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F1/3203 , G06F1/3293 , G06F9/30189 , G06F9/3885 , Y02D10/122
摘要： A processor for a portable electronic device. The processor includes a RISC (reduced instruction set computing) core a CISC (complex instruction set computing) core, a video accelerator circuit and an audio accelerator circuit. Each of the video and audio accelerator circuits are coupled to both the RISC and CISC cores, with both cores and both accelerator circuit being incorporated into a single integrated circuit. In a first plurality of operational modes, the RISC core is active, while the CISC core is in one of a sleep state or a power off state. In a second plurality of modes, both the RISC and CISC cores are active.
摘要翻译：一种用于便携式电子设备的处理器。处理器包括RISC（精简指令集计算）核心，CISC（复杂指令集计算）核心，视频加速器电路和音频加速器电路。每个视频和音频加速器电路都耦合到RISC和CISC核心，两个核心和两个加速器电路都被并入单个集成电路中。在第一多个操作模式中，RISC核心是活动的，而CISC核心处于休眠状态或断电状态之一。在第二种多种模式中，RISC和CISC内核都是活动的。

125. 发明授权

US07760840B2 Clock-signal adjusting method and device 有权
标题翻译：时钟信号调整方法及装置
公开(公告)号：US07760840B2
公开(公告)日：2010-07-20
申请号：US11464756
申请日：2006-08-15
申请人： Chi Chang
发明人： Chi Chang
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/091 , H03L7/113 , H03L7/14 , H04L7/033
摘要： A clock-signal adjusting method and device is used for adjusting a frequency of a clock signal according to a frequency of an input data. The input data is sampled with a sampling frequency m times of the clock frequency to obtain a data transition waveform indicating data transition timing distribution. A unitary bit time of the input data is divided into m zones. A frequency relationship between the clock signal and the input data is determined according to a shift of the data transition waveform relative to the zones. The frequency of the clock signal is adjusted according to the frequency relationship.
摘要翻译：时钟信号调整方法和装置用于根据输入数据的频率调整时钟信号的频率。输入数据以时钟频率的m倍的采样频率进行采样，以获得指示数据转换时序分布的数据转换波形。输入数据的单位时间分为m个区。时钟信号和输入数据之间的频率关系根据数据转换波形相对于各个区域的偏移来确定。根据频率关系调整时钟信号的频率。

126. 发明申请

US20100077248A1 CLOCK GENERATING DEVICE, METHOD THEREOF AND COMPUTER SYSTEM USING THE SAME BACKGROUND OF THE INVENTION 有权
标题翻译：时钟产生装置，其方法和使用该方法的计算机系统技术领域
公开(公告)号：US20100077248A1
公开(公告)日：2010-03-25
申请号：US12564907
申请日：2009-09-22
申请人： Ching-Yen Wu , Chi Chang
发明人： Ching-Yen Wu , Chi Chang
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.
摘要翻译：提供了一种时钟发生装置及其方法以及使用其的计算机系统。时钟发生装置包括PLL模块和调谐模块。 PLL模块接收参考时钟信号，并根据参考时钟信号和反馈信号之间的相位差产生输出时钟信号作为计算机系统的基本时钟。 PLL模块包括根据控制信号调整固有分频比的分频器，并对输出时钟信号进行分频处理以产生反馈信号。与PLL模块耦合的调谐模块根据CPU的VID和反馈信号和参考时钟之一产生控制信号。因此，可以同步调整作为计算机系统中的基本频率的输出时钟信号的组件的操作频率。

127. 发明申请

US20090061631A1 GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT 有权
标题翻译：顶部氧化物改进的顶部氧化物替换
公开(公告)号：US20090061631A1
公开(公告)日：2009-03-05
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

128. 发明申请

US20090049327A1 COMPUTER SYSTEM WITH ADJUSTABLE DATA TRANSMISSION RATE 有权
标题翻译：具有可调数据传输速率的计算机系统
公开(公告)号：US20090049327A1
公开(公告)日：2009-02-19
申请号：US12191411
申请日：2008-08-14
申请人： Chien-Ping Chung , Cheng-Wei Huang , Chi Chang
发明人： Chien-Ping Chung , Cheng-Wei Huang , Chi Chang
IPC分类号： G06F5/06
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/126 , Y02D10/151
摘要： A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.
摘要翻译：计算机系统具有在CPU和其核心逻辑芯片之间的可调数据传输速率。在计算机系统中，CPU具有响应于由核心逻辑芯片发出的功率管理控制信号而调整的功率状态。为了调整CPU和核心逻辑芯片之间的数据传输速率，首先确定功率管理控制信号从第一时间段到第二时间段的断言时间的改变以获得索引值。数据传输速率根据指标值增减。

129. 发明授权

US07288809B1 Flash memory with buried bit lines 有权
标题翻译：闪存与埋位线
公开(公告)号：US07288809B1
公开(公告)日：2007-10-30
申请号：US10738322
申请日：2003-12-16
申请人： Richard M. Fastow , Chi Chang , Sheung Hee Park
发明人： Richard M. Fastow , Chi Chang , Sheung Hee Park
IPC分类号： H01L29/72
CPC分类号： H01L27/115 , H01L27/11521
摘要： A memory cell and a method of forming the same are described. The memory cell is formed on a substrate. The memory cell includes a floating gate that is formed at least in part within the substrate. A bit line region is formed within the substrate in proximity to the floating gate. Because of the configuration of the bit line and the floating gate, memory cells can be located closer to each other, increasing the density of memory cells in a memory array.
摘要翻译：描述了存储单元及其形成方法。存储单元形成在基板上。存储单元包括至少部分地形成在衬底内的浮栅。位于衬底内的位线区域靠近浮动栅极。由于位线和浮动栅的配置，存储单元可以位于彼此更靠近，增加了存储器阵列中存储单元的密度。

130. 发明申请

US20070046109A1 Miniature linear motor driving device and auto-focus lens device using the same 审中-公开
标题翻译：微型直线电机驱动装置及使用其的自动对焦透镜装置
公开(公告)号：US20070046109A1
公开(公告)日：2007-03-01
申请号：US11266295
申请日：2005-11-04
申请人： Wen Jen Ho , Chi Chang
发明人： Wen Jen Ho , Chi Chang
IPC分类号： H02K41/00 , G02B15/14
CPC分类号： H02K41/0352 , G02B7/08
摘要： A miniature linear motor driving device for lens focusing is disclosed. Said driving device comprises a holder, at least a driving coil, and at least a magnetic guide rail. The holder is disposed with at least a guide hole and can be used to accommodate the lens unit. The driving coil is wound around the periphery of guide hole. The magnetic guide rail is secured through the guide hole and formed with a first polarity and a second polarity opposing each other at each end. The holder engages in linear displacement along the magnetic guide rail. A predetermined magnetic force is generated by supplying current to said driving coil, which interacts with the polarities at both ends of magnetic guide rail to push the holder to move linearly along the magnetic guide rail.
摘要翻译：公开了一种用于透镜聚焦的微型线性电动机驱动装置。所述驱动装置包括保持器，至少驱动线圈和至少磁导轨。保持器设置有至少一个引导孔，并且可以用于容纳透镜单元。驱动线圈缠绕在导向孔周边。磁导轨通过引导孔固定，并形成在每一端彼此相对的第一极性和第二极性。保持器沿着磁导轨进行线性位移。通过向所述驱动线圈提供电流而产生预定的磁力，所述驱动线圈与磁导轨两端的极性相互作用，以推动保持件沿着磁导轨线性移动。

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