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121. 发明申请

US20060131635A1 Flash memory device and manufacturing method thereof 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US20060131635A1
公开(公告)日：2006-06-22
申请号：US11018536
申请日：2004-12-20
申请人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
发明人： Erh-Kun Lai , Hang-Ting Lue , Yen-Hao Shih , Chia-Hua Ho
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11521 , H01L29/42376
摘要： A method of manufacturing a flash memory device is provided. Multiple stack structures each comprising a tunneling oxide layer and a first conductive layer are formed over a substrate. Thereafter, multiple embedded doping regions is formed in the substrate between the stack structures. A dielectric layer is formed over the substrate to cover the stack structures and then the dielectric layer is etched back and a portion of dielectric layer is remained on the stack structures. Using a portion of the remaining dielectric layer as a mask, a portion of the first conductive layer is removed. An inter-layer dielectric layer and a second conductive layer are sequentially formed over the first conductive layer. Because a self-aligned process is used to define the floating gate and the floating gate has a narrow-top/wide-bottom configuration, the fabrication process is simplified and the coupling ratio of the stack gate is increased.
摘要翻译：提供一种制造闪速存储器件的方法。在衬底上形成各自包括隧穿氧化物层和第一导电层的堆叠结构。此后，在堆叠结构之间的衬底中形成多个嵌入的掺杂区域。介电层形成在衬底上以覆盖堆叠结构，然后电介质层被回蚀刻，并且介电层的一部分保留在堆叠结构上。使用剩余电介质层的一部分作为掩模，去除第一导电层的一部分。在第一导电层上依次形成层间电介质层和第二导电层。由于使用自对准工艺来定义浮动栅极，并且浮栅具有窄顶/宽底部配置，因此简化了制造工艺，并且增加了堆叠栅极的耦合比。

122. 发明申请

US20060001075A1 Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same 有权
标题翻译：具有两个分离的非导电电荷捕获插入物的电荷俘获存储器件及其制造方法
公开(公告)号：US20060001075A1
公开(公告)日：2006-01-05
申请号：US10884483
申请日：2004-07-01
申请人： Yen-Hao Shih
发明人： Yen-Hao Shih
IPC分类号： H01L29/768 , H01L21/8238
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two junctions. A polysilicon gate is defined over the GOX. A layer of bottom oxide (BOX) is grown on top of the silicon substrate and a conformal layer of top oxide (TOX) is grown along the bottom and the sidewalls of the polysilicon gate. Two charge trapping inserts are located beside the GOX and between the BOX and the TOX. The polysilicon gate needs to be at least partially over each of the two charge trapping inserts. The charge trapping inserts are made from a non-conductive charge trapping material. A method for fabricating such a device is also described.
摘要翻译：公开了具有两个分开的非导电电荷捕获插入物的电荷捕获存储器件。电荷捕获存储器件具有带有两个结的硅衬底。在硅衬底的顶部和两个结之间形成栅极氧化物（GOX）。在GOX上定义了多晶硅栅极。在硅衬底的顶部上生长一层底部氧化物（BOX），沿多晶硅栅极的底部和侧壁生长顶部氧化物（TOX）的共形层。两个充电陷阱插件位于GOX旁边和BOX和TOX之间。多晶硅栅极需要至少部分地在两个电荷捕获插入物中的每一个上。电荷捕获插入物由非导电电荷捕获材料制成。还描述了制造这种装置的方法。

123. 发明申请

US20050236613A1 QUANTUM-WELL MEMORY DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：量子阱存储器件及其制造方法
公开(公告)号：US20050236613A1
公开(公告)日：2005-10-27
申请号：US10831431
申请日：2004-04-23
申请人： Yen-Hao Shih
发明人： Yen-Hao Shih
IPC分类号： H01L21/28 , H01L29/06 , H01L29/423 , H01L29/788
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/7887
摘要： A quantum-well memory device and method is provided. The quantum-well memory device includes a substrate with two junctions. A sandwiched gate insulator is formed on top of the substrate and extended in length between the two junctions. The sandwiched gate insulator has a top layer, a middle layer, and a bottom layer. The middle layer is more soluble to an acid etch than the top and the bottom layer of the gate insulator. Polysilicon inserts are defined at the undercuts formed by selectively and self-limitedly etching the sidewalls of the middle layer of the gate insulator. The polysilicon inserts are positioned beside the middle layer and between the top layer and the bottom layer of the gate insulator. A method for fabricating such a device is also described.
摘要翻译：提供量子阱存储器件和方法。量子阱存储器件包括具有两个结的衬底。夹层栅极绝缘体形成在衬底的顶部并且在两个结之间的长度上延伸。夹层绝缘体具有顶层，中间层和底层。中间层比栅极绝缘体的顶层和底层更易溶于酸蚀刻。多晶硅插入件限定在通过选择性地且自限制地蚀刻栅极绝缘体的中间层的侧壁形成的切口。多晶硅插入件位于中间层的旁边，并且位于栅极绝缘体的顶层和底层之间。还描述了制造这种装置的方法。

124. 发明授权

US06352939B1 Method for improving the electrical properties of a gate oxide 有权
标题翻译：改善栅极氧化物的电性能的方法
公开(公告)号：US06352939B1
公开(公告)日：2002-03-05
申请号：US09506850
申请日：2000-02-17
申请人： Jenn-Gwo Hwu , Yen-Hao Shih
发明人： Jenn-Gwo Hwu , Yen-Hao Shih
IPC分类号： H01L21302
CPC分类号： H01L21/28185 , H01L21/02238 , H01L21/02255 , H01L21/02343 , H01L21/28202 , H01L21/28211 , H01L21/31662 , H01L21/326 , H01L29/517 , H01L29/518
摘要： A method for improving the electrical properties of a gate oxide is disclosed. The method includes the steps of providing a silicon wafer with a gate oxide formed thereon, providing a platinum plate, immersing the silicon wafer and the platinum plate in a chemical solution with a relatively high electrical conductivity, respectively connecting the silicon wafer and the platinum plate to the negative terminal and the positive terminal of a current source, inducing an electron current to flow from the negative terminal of the current source through the silicon wafer to the platinum plate, removing the silicon wafer from the chemical solution and removing the residual chemical solution from the surface of the gate oxide, and treating the gate oxide with an annealing process.
摘要翻译：公开了一种用于改善栅极氧化物的电性能的方法。该方法包括以下步骤：提供硅晶片上形成的栅极氧化物，提供铂板，将硅晶片和铂板浸入具有较高导电率的化学溶液中，分别将硅晶片和铂板引起电流源的负极端子和正极端子，使电子电流从电流源的负极通过硅晶片流向铂板，从化学溶液中除去硅晶片，并除去残留的化学溶液从栅极氧化物的表面，并用退火工艺处理栅极氧化物。

125. 发明授权

US08847299B2 Non-volatile memory and non-volatile memory cell having asymmetrical doped structure 有权
标题翻译：具有非对称掺杂结构的非易失性存储器和非易失性存储单元
公开(公告)号：US08847299B2
公开(公告)日：2014-09-30
申请号：US12017064
申请日：2008-01-21
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih
IPC分类号： H01L29/76 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792
摘要： A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.
摘要翻译：一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。电荷捕获层和控制栅极设置在衬底上。电介质层设置在基板，电荷俘获层和控制栅极之间。源极和漏极设置在电荷俘获层的每一侧上的衬底中。轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

126. 发明申请

US20140054535A1 SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
标题翻译：具有改进位线电容的半导体结构
公开(公告)号：US20140054535A1
公开(公告)日：2014-02-27
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

127. 发明授权

US08581327B2 Memory and manufacturing method thereof 有权
公开(公告)号：US08581327B2
公开(公告)日：2013-11-12
申请号：US12974093
申请日：2010-12-21
申请人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
发明人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/66545 , H01L29/66583 , H01L29/7923
摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

128. 发明授权

US07973366B2 Dual-gate, sonos, non-volatile memory cells and arrays thereof 有权
标题翻译：双栅极，超声波，非易失性存储单元及其阵列
公开(公告)号：US07973366B2
公开(公告)日：2011-07-05
申请号：US11352788
申请日：2006-02-13
申请人： Chia-Hua Ho , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Chia-Hua Ho , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , G11C16/0475 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.
摘要翻译：存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

129. 发明申请

US20110089480A1 MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：内存及其制造方法
公开(公告)号：US20110089480A1
公开(公告)日：2011-04-21
申请号：US12974093
申请日：2010-12-21
申请人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
发明人： Erh-Kun Lai , Yen-Hao Shih , Ling-Wu Yang , Chun-Min Cheng
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/66545 , H01L29/66583 , H01L29/7923
摘要： A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.
摘要翻译：提供具有隔离双存储单元的存储器。第一隔离壁和第二隔离壁分别设置在基板上的源极和漏极之间。隔离底层和多晶硅层有序地设置在第一和第二隔离壁之间的衬底上。第一电荷存储结构和第一栅极有序地设置在第一隔离壁和源极之间的衬底上。第二电荷存储结构和第二栅极有序地设置在第二隔离壁和漏极之间的衬底上。布置在多晶硅层上的字线，第一栅极，第二栅极，第一隔离壁和第二隔离壁电连接到第一栅极，第二栅极和多晶硅层。

130. 发明申请

US20110073937A1 Method for Fabricating a Charge Trapping Memory Device 有权
标题翻译：制造电荷俘获存储器件的方法
公开(公告)号：US20110073937A1
公开(公告)日：2011-03-31
申请号：US12962361
申请日：2010-12-07
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

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