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121. 发明申请

US20060186456A1 NVM cell on SOI and method of manufacture 审中-公开
标题翻译： NVM单元在SOI及其制造方法
公开(公告)号：US20060186456A1
公开(公告)日：2006-08-24
申请号：US11060996
申请日：2005-02-18
申请人： James Burnett , Ramachandran Muralidhar
发明人： James Burnett , Ramachandran Muralidhar
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , H01L21/26586 , H01L27/115 , H01L27/11521 , H01L29/1083 , H01L29/7881
摘要： A non-volatile memory (NVM) device formed in a semiconductor-on-insulator (SOI) substrate has a trap region on the source side only to speed up the process of programming. During programming of an NVM device in partially depleted SOI, holes are generated that slow down the formation of electrons hot enough to jump to the storage layer of the NVM. To reduce this effect, the trap region is formed below the lightly-doped portion of the source region and preferably extends to an area under the gate on the source side. This can be achieved using an angled implant of a neutral impurity, such as xenon, argon, or germanium, while masking the drain side. The trap region thus extends under the gate on the source side to recombine with holes that are generated during programming. The trap region also extends to contact the source.
摘要翻译：形成在绝缘体上半导体（SOI））衬底中的非易失性存储器（NVM）器件在源极上具有陷阱区域，仅用于加速编程过程。在部分耗尽的SOI中的NVM器件的编程期间，产生空穴，其减慢热到足以跳到NVM的存储层的电子的形成。为了减小这种影响，陷波区域形成在源极区域的轻掺杂部分下方，优选地延伸到源极侧的栅极下方的区域。这可以使用中性杂质（例如氙，氩或锗）的倾斜注入来实现，同时掩蔽漏极侧。陷阱区域因此在源极侧的栅极下方与编程期间产生的孔重新组合。陷阱区域也延伸以接触源。

122. 发明申请

US20050282345A1 Transistor with vertical dielectric structure 有权
标题翻译：具有垂直电介质结构的晶体管
公开(公告)号：US20050282345A1
公开(公告)日：2005-12-22
申请号：US10871772
申请日：2004-06-18
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/786 , H01L29/788
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/66795 , H01L29/66825 , H01L29/785 , H01L29/7887
摘要： A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.
摘要翻译：一种具有垂直结构（113）的晶体管（103），其包括半导体结构（109）下面的电介质结构（201）。半导体结构包括沟道区（731）和源极/漏极区（707,709）。晶体管包括具有与半导体结构横向相邻的部分和与电介质结构横向相邻的部分的栅极结构（705,703）。在一个实施例中，栅极结构是浮动栅极结构，其中控制栅极结构（719）还包括横向邻近电介质结构的部分和与半导体结构横向相邻的部分。在一些示例中，具有浮置栅极的一部分和与电介质结构相邻的控制栅极的一部分用于将控制栅极增加到浮置栅极电容，而不显着增加浮置栅极到沟道区的电容。

123. 发明授权

US06967143B2 Semiconductor fabrication process with asymmetrical conductive spacers 失效
公开(公告)号：US06967143B2
公开(公告)日：2005-11-22
申请号：US10427141
申请日：2003-04-30
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/7842 , Y10S257/90
摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

124. 发明授权

US06964902B2 Method for removing nanoclusters from selected regions 失效
公开(公告)号：US06964902B2
公开(公告)日：2005-11-15
申请号：US10787510
申请日：2004-02-26
申请人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
发明人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

125. 发明授权

US06958265B2 Semiconductor device with nanoclusters 有权
标题翻译：具有纳米团簇的半导体器件
公开(公告)号：US06958265B2
公开(公告)日：2005-10-25
申请号：US10663621
申请日：2003-09-16
申请人： Robert F. Steimle , Ramachandran Muralidhar , Wayne M. Paulson , Rajesh A. Rao , Bruce E. White, Jr. , Erwin J. Prinz
发明人： Robert F. Steimle , Ramachandran Muralidhar , Wayne M. Paulson , Rajesh A. Rao , Bruce E. White, Jr. , Erwin J. Prinz
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/115 , H01L29/423
CPC分类号： B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.
摘要翻译：用纳米团簇形成装置的方法。该方法包括形成纳米团簇（例如硅纳米晶体）并在纳米簇上形成氧化阻挡层，以在随后形成器件的电介质期间抑制氧化剂氧化纳米团簇。在形成电介质后，去除至少一部分氧化阻挡层。在一个示例中，该器件是其中纳米团簇用作存储器的电荷存储晶体管的电荷存储位置的存储器。在该实施例中，氧化阻挡层由于形成用于存储器的高压晶体管的栅极电介质而保护纳米团簇免受氧化剂的影响。

126. 发明申请

US20050098822A1 Transistor having three electrically isolated electrodes and method of formation 有权
标题翻译：具有三个电隔离电极的晶体管和形成方法
公开(公告)号：US20050098822A1
公开(公告)日：2005-05-12
申请号：US10705317
申请日：2003-11-10
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/788 , H01L29/76
CPC分类号： H01L27/108 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/10826 , H01L27/10879 , H01L27/10894 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881
摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.
摘要翻译：晶体管（10）形成有三个可分别控制的栅极（44,42,18）。三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。通道侧壁上的电介质可以不同于通道顶部的电介质。选择性地制造到源极，漏极和三个栅极的电接触。通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

127. 发明授权

US06350690B1 Process for achieving full global planarization during CMP of damascene semiconductor structures 有权
标题翻译：在大马士革半导体结构的CMP期间实现全局全局平坦化的工艺
公开(公告)号：US06350690B1
公开(公告)日：2002-02-26
申请号：US09288646
申请日：1999-04-09
申请人： Gary Paul Schwartz , Ramachandran Muralidhar , Stephen Hymes
发明人： Gary Paul Schwartz , Ramachandran Muralidhar , Stephen Hymes
IPC分类号： H01L21461
CPC分类号： H01L21/7684 , H01L21/3212
摘要： Described is a process for using chemical-mechanical planarization in the manufacture of Damascene structures that substantially reduces unwanted topography. The process is implemented in two stages to separate bulk metal removal and interface clearing. In stage 1 a top metal layer is planarized both globally and locally by CMP removal at a high rate of the preponderance of overlying metal, without penetrating to dielectric or barrier materials and with a minimum of CMP-generated global topography. For stage 2, the slurry is formulated with a 1:1:1 removal rate selectivity as to the metal/barrier/dielectric materials, the object being to preserve the highly flat topography achieved in stage 1.
摘要翻译：描述了在大马士革结构的制造中使用化学机械平面化的方法，其大大减少了不想要的形貌。该过程分两个阶段实现，以分离大量金属去除和界面清除。在阶段1中，顶部金属层通过在高覆盖金属的优势的高速率下通过CMP去除而全局地和局部地平坦化，而不渗透到电介质或阻挡材料，并且具有最小的CMP生成的全局形貌。对于阶段2，对于金属/屏障/电介质材料，浆料以1:1:1的去除速率选择性配制，目的是保持在阶段1中实现的高度平坦的形貌。

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