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121. 发明授权

US5293560A Multi-state flash EEPROM system using incremental programing and erasing methods 失效
标题翻译：多状态闪存EEPROM系统采用增量编程和擦除方式
公开(公告)号：US5293560A
公开(公告)日：1994-03-08
申请号：US970949
申请日：1992-11-03
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , G11C29/00 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/349 , G11C16/3495 , G11C29/765 , G11C29/82 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L29/7881 , H01L29/7885 , G11C2211/5613 , G11C2211/5631 , G11C2211/5634 , G11C2211/5644 , G11C29/00
摘要： A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
摘要翻译：由电可编程只读存储器（EPROM）或闪存电可擦除和可编程只读存储器（EEPROM）单元组成的存储器系统。智能编程技术允许每个存储器单元存储比通常的一位信息。通过建立单元被编程的两个以上不同的阈值状态，多个位被存储在单元中。在其编程期间，一系列增加电压的脉冲被施加到每个寻址的存储器单元，在脉冲之间读取单元的状态。脉冲在所寻址的单元达到其期望状态时终止，或达到预设的最大脉冲数。智能擦除算法可延长存储单元的使用寿命。一系列脉冲也被施加到被擦除的单元块，在脉冲之间读取至少一个单元的样本数的状态。当读取的单元被确定为已经达到完全擦除状态或者已经发生了许多其他条件中的一种时，停止擦除过程。使用这些各种特征提供了具有非常高的存储密度和长寿命的存储器，使得其作为固态存储器代替计算机系统中的磁盘存储装置是特别有用的。

122. 发明授权

US5268318A Highly compact EPROM and flash EEPROM devices 失效
公开(公告)号：US5268318A
公开(公告)日：1993-12-07
申请号：US776826
申请日：1991-10-15
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , G11C29/00 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/60
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/349 , G11C16/3495 , G11C29/765 , G11C29/82 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L29/7881 , H01L29/7885 , G11C2211/5613 , G11C2211/5631 , G11C2211/5634 , G11C2211/5644 , G11C29/00 , Y10S438/972
摘要： Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

123. 发明授权

US5198380A Method of highly compact EPROM and flash EEPROM devices 失效
标题翻译：高度紧凑的EPROM和闪存EEPROM器件的方法
公开(公告)号：US5198380A
公开(公告)日：1993-03-30
申请号：US381139
申请日：1989-07-17
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , G11C29/00 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/349 , G11C16/3495 , G11C29/765 , G11C29/82 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L29/7881 , H01L29/7885 , G11C2211/5613 , G11C2211/5631 , G11C2211/5634 , G11C2211/5644 , G11C29/00
摘要： Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
摘要翻译：电气可编程只读存储器（EPROM）和闪存电可擦除可编程只读存储器（EEPROM）的结构，制造方法和使用方法包括分离通道和其他单元配置。元件和协调制造工艺的布置提供元件的自我对准。智能编程技术允许每个存储器单元存储比通常的一位信息。智能擦除算法可延长存储单元的使用寿命。使用这些各种特征提供具有非常高的存储密度和长寿命的存储器，使得其作为固态存储器代替计算机系统中的磁盘存储装置是特别有用的。

124. 发明授权

US5172338A Multi-state EEprom read and write circuits and techniques 失效
标题翻译：多状态EEprom读写电路和技术
公开(公告)号：US5172338A
公开(公告)日：1992-12-15
申请号：US508273
申请日：1990-04-11
申请人： Sanjay Mehrotra , Eliyahou Harari , Winston Lee
发明人： Sanjay Mehrotra , Eliyahou Harari , Winston Lee
IPC分类号： G11C16/02 , G01R31/28 , G11C7/00 , G11C11/00 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/16 , G11C16/28 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C7/04 , G11C2211/5621 , G11C2211/5631 , G11C2211/5634 , G11C2211/5645
摘要： Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.
摘要翻译： EEprom存储器的读，写和擦除电路和技术的改进使非易失性多态存储器能够在更长的时间内以更高的性能运行。在用于正常读取和用于读取或擦除之间的读取和读取的改进电路进行验证之前，相对于由对应的一组参考单元提供的一组阈值电平进行读取，所述一组参考单元紧密地跟踪和调整由存储器呈现的变化细胞。在一个实施例中，存储器单元的每个闪存扇区具有其自己的用于读取扇区中的单元的参考单元，并且对于用作主参考的整个存储器芯片也存在一组参考单元。在另一个实施例中，通过一对多电流镜像电路同时进行相对于一组阈值电平的读取。在改进的写入或擦除电路中，写入或擦除的数据的验证一次在一组存储器单元上并行完成，并且电路选择性地禁止对已经被正确验证的那些单元进一步写入或擦除。其他改进包括对擦除后的基准状态进行编程，独立和可变的电源为EEprom存储器单元的控制栅极。

125. 发明授权

US4998220A EEPROM with improved erase structure 失效
标题翻译： EEPROM具有改进的擦除结构
公开(公告)号：US4998220A
公开(公告)日：1991-03-05
申请号：US189874
申请日：1988-05-03
申请人： Boaz Eitan , Eliyahou Harari
发明人： Boaz Eitan , Eliyahou Harari
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/11519 , G11C16/0425 , H01L27/115
摘要： An electrically erasable programmable read only memory (EEPROM) constructed in accordance with the invention includes a source, a drain, a channel region formed between the source and drain, a floating gate extending over a first portion of the channel region but not a second portion of the channel region, and a control gate extending over a first portion of the floating gate and the second portion of the channel region. Of importance, the EEPROM includes an erase gate which is formed concurrently with the control gate and extending over a second portion of the floating gate. Because the erase gate is formed concurrently with the control gate, the process used to form the EEPROM requires only two layers of polysilicon. Also, because electrons tunnel between the floating gate and the erase gate during electrical erase instead of between the floating gate and the drain, there is no PN junction breakdown during electrical erase and therefore, the EEPROM array can be erased using a low current voltage supply.
摘要翻译：根据本发明构造的电可擦除可编程只读存储器（EEPROM）包括源极，漏极，形成在源极和漏极之间的沟道区域;浮置栅极，其延伸在沟道区域的第一部分上而不是第二部分以及在所述浮动栅极的第一部分和所述沟道区域的第二部分之上延伸的控制栅极。重要的是，EEPROM包括与控制栅同时形成并在浮动栅极的第二部分上延伸的擦除栅极。由于擦除栅极与控制栅极同时形成，所以用于形成EEPROM的工艺只需要两层多晶硅。而且，因为在电擦除期间电子在浮动栅极和擦除栅极之间隧穿，而不是浮置栅极和漏极之间，所以在电擦除期间不存在PN结击穿，因此，EEPROM阵列可以使用低电流电压源。

126. 发明授权

US4448400A Highly scalable dynamic RAM cell with self-signal amplification 失效
标题翻译：高度可扩展的动态RAM单元，具有自我信号放大
公开(公告)号：US4448400A
公开(公告)日：1984-05-15
申请号：US355986
申请日：1982-03-08
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/56 , H01L23/556 , H01L27/085 , H01L27/108 , H01L27/115 , G11C11/40
CPC分类号： H01L27/085 , G11C11/565 , H01L23/556 , H01L27/108 , H01L27/115 , H01L2924/0002 , H01L2924/3011
摘要： A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening to a diffused region in the substrate. This diffusion serves as a junction isolated storage node. This storage node can be charged or discharged through an MOS write transistor. The first electrode is capacitively coupled to a field plate held at a first potential. A control gate formed in a second electrode controls conduction through the write transistor and also allows selective reading in an array of read transistors. Nondestructive read can be achieved together with transistor amplification of the charge stored on the first electrode.
摘要翻译：动态RAM存储单元包括MOS读取晶体管，其导电性状态由覆盖读取晶体管沟道区的第一电极上的电荷状态决定。第一电极通过埋入触点开口连接到衬底中的扩散区域。该扩散用作结隔离存储节点。该存储节点可以通过MOS写入晶体管被充电或放电。第一电极电容耦合到保持在第一电位的场板。形成在第二电极中的控制栅极控制通过写入晶体管的导通，并且还允许读取晶体管阵列中的选择性读取。非破坏性读取可以与存储在第一电极上的电荷的晶体管放大一起实现。所述第二区域和所述第三区域之间的第一部分和通过所述第三区域和所述第五区域之间的间隔测量的沟道长度的写入晶体管，以及形成在所述第五区域和所述第一区域之间的存储结。通过在将字线驱动期间将第三区域上的电压改变为正或负电压时，第一电极上的电荷变化，从而改变读字晶体管的阈值电压，如字线所示。可以使用如所描述的多个存储单元来形成阵列，并且通过改变所选择的存储单元中的字线或第三区与第一电极之间的电容耦合，或者通过改变施加到第三在所述第一电极存储电荷期间的写入期间，该特定单元可以在读取操作期间用作参考单元。

127. 发明授权

US4327477A Electron beam annealing of metal step coverage 失效
标题翻译：电子束退火金属台阶覆盖
公开(公告)号：US4327477A
公开(公告)日：1982-05-04
申请号：US169559
申请日：1980-07-17
申请人： Giora Yaron , Eliyahou Harari , LaVerne D. Hess , Yueh Y. Ma
发明人： Giora Yaron , Eliyahou Harari , LaVerne D. Hess , Yueh Y. Ma
IPC分类号： H01L21/263 , H01L21/268 , H01L21/321 , B05D3/06
CPC分类号： H01L21/2636 , H01L21/268 , H01L21/321 , Y10S148/046
摘要： Defects in the metal step coverage of a thin film semiconductor device are removed by annealing the metal layer with a pulsed electron beam.
摘要翻译：通过用脉冲电子束退火金属层来去除薄膜半导体器件的金属层覆盖的缺陷。

128. 发明授权

US4316264A Uniquely accessed RAM 失效
标题翻译：独特访问的RAM
公开(公告)号：US4316264A
公开(公告)日：1982-02-16
申请号：US110405
申请日：1980-01-08
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/413 , G11C11/412 , G11C11/419 , G11C7/00 , G11C8/00
CPC分类号： G11C11/412 , G11C11/419
摘要： Each bistable cell of a memory matrix is uniquely accessed through a row transistor and a column transistor connected in series between one node of the bistable cell and the data-in. During WRITE, a single row is accessed activating all of the gates on the row transistors of that row, and a single column is accessed activating all of the gates on the column transistors of that column. Only the addressed cell at the intersection of the accessed row and column has both the row and column transistors turned on establishing a conductive path to the data line. All of the remaining cells on the accessed row and column have only one of their access transistors turned on. The other access transistor of these partially accessed cells remains non-conductive. The data-in on the data line is either high ("1") or low ("0") driving the addressed cell into one of two storage states. During READ only the addressed cell at the intersection of the accessed row and column has a conductive path to the high read voltage on the data line. The storage state of the addressed cell causes the data line voltage to either load down or to remain high. Write and read disturb are prevented because all of the remaining cells have at least one of their two access transistors turned off. The write and read isolation reduces the cell stability requirement to a very small trickle current necessary to maintain the node capacitance in the cell. The charge on these capacitances may be replenished periodically by charge pumping the load device. Read disturb of the accessed cell is avoided by employing a regenerative sense amplifier which restores the accessed data after each read cycle.
摘要翻译：存储器矩阵的每个双稳态单元通过串联在双稳态单元的一个节点和数据输入之间的行晶体管和列晶体管独特地访问。在写入期间，单行访问激活该行的行晶体管上的所有栅极，并且访问单个列来激活该列的列晶体管上的所有栅极。只有所访问的行和列的交叉点处的寻址单元格都导通了行和列晶体管，建立到数据线的导电路径。所访问的行和列上的所有剩余单元格只有一个访问晶体管导通。这些部分访问的单元的另一个存取晶体管保持不导通。数据线上的数据输入是高（“1”）或低（“0”），将寻址的单元驱动为两种存储状态之一。在READ期间，所访问的行和列的交点处的寻址单元具有到数据线上的高读取电压的导通路径。所寻址单元的存储状态导致数据线电压下降或保持高电平。阻止写入和读取干扰，因为所有剩余的单元都具有两个存取晶体管中的至少一个截止。写和读隔离将电池稳定性要求降低到维持电池中节点电容所需的非常小的涓流电流。这些电容的电荷可以通过对负载装置进行充电来定期补充。通过使用在每个读取周期之后恢复所访问的数据的再生感测放大器来避免所访问单元的读取干扰。

129. 发明授权

US4132904A Volatile/non-volatile logic latch circuit 失效
标题翻译：易失性/非易失逻辑锁存电路
公开(公告)号：US4132904A
公开(公告)日：1979-01-02
申请号：US819794
申请日：1977-07-28
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C14/00 , H01L27/11 , H01L29/788 , H03K3/356 , G11C11/40
CPC分类号： H01L29/7883 , G11C14/00 , H01L27/11 , H01L27/1104 , H01L27/1112 , H03K3/356008
摘要： There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such it acts as an ordinary semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. The novel results of the cell described are achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state. Therefore, if power is removed and then returned, the latch will always settle into a state dictated by the final state that existed in the latch before the high voltage pulse was applied. In this way the variable threshold elements of the latch cell make it a non-volatile memory element. It can be used either as a read/write memory, using its latch property, or as a read-only memory, using the variable threshold transistors to cause it to always latch in a predetermined manner.
摘要翻译：描述了以独特的方式电连接在一起以形成锁存器的固定阈值和可变阈值晶体管的逻辑元件。可以通过将某些内部节点保持在高电压或低电压电平来使闩锁保持数据。因此，它作为普通半导体存储器锁存器，其数据可以通过外部覆盖锁存单元的内部电压电平来改变。所描述的单元的新颖结果是通过用特殊构造的晶体管代替锁存器中的一个或几个晶体管，其阈值电压在其栅极和衬底之间施加相对较高的电压脉冲时可以升高或降低来实现。通过施加这样的高电压脉冲，存储在锁存器中的数据可以转换成唯一地表示初始锁存状态的可变阈值晶体管的受控阈值偏移。因此，如果功率被去除然后返回，则锁存器将总是处于由施加高电压脉冲之前存在于锁存器中的最终状态所指示的状态。以这种方式，锁存单元的可变阈值元件使其成为非易失性存储元件。它可以用作读/写存储器，使用其锁存属性，或者作为只读存储器，使用可变阈值晶体管使其总是以预定方式锁存。

130. 发明授权

US4047974A Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states 失效
标题翻译：用于利用注入的离子来制造非挥发性场效应半导体存储器结构以诱发俘获状态的方法
公开(公告)号：US4047974A
公开(公告)日：1977-09-13
申请号：US645150
申请日：1975-12-30
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/3115 , H01L29/788 , H01L29/792 , H01L21/265 , H01L21/324 , H01L29/78
CPC分类号： H01L21/28282 , H01L21/31155 , H01L29/792 , Y10S438/91
摘要： Disclosed is a non-volatile field effect information storage device which can be electrically written and erased. It consists of an insulated gate field effect transistor having a single gate dielectric material formed in two stages. The gate dielectric is made up of two adjacent layers of silicon dioxide, one of which is relatively thin and adjacent to the semiconductor substrate, while the other is relatively thick and implanted with ions at controlled depths and dosages near the interface with the first silicon dioxide layer. With the application of an appropriate control voltage on the gate structure, charges from the adjacent transistor channel region tunnel through the relatively thin layer of silicon dioxide and become stored in the trapping sites introduced by the implanted ions located in the second layer of silicon dioxide and very near the interface between the two silicon dioxide layers. While there, the charges control the conductivity of the channel, and thus the logic state of the transistor.
摘要翻译：公开了一种可以电写入和擦除的非易失性场效应信息存储装置。它由一个绝缘栅场效应晶体管组成，具有分两层形成的单栅电介质材料。栅极电介质由两个相邻的二氧化硅层组成，其中一个相对较薄并且与半导体衬底相邻，而另一个相对较厚，并且以受控的深度和与第一二氧化硅的界面附近的剂量注入离子层。通过在栅极结构上施加适当的控制电压，来自相邻晶体管沟道区域隧道的电荷穿过相对较薄的二氧化硅层并且被储存在由位于第二层二氧化硅中的注入离子引入的俘获位置，非常靠近两个二氧化硅层之间的界面。而在那里，电荷控制通道的电导率，从而控制晶体管的逻辑状态。

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