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121. 发明申请

US20060092363A1 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US20060092363A1
公开(公告)日：2006-05-04
申请号：US11255107
申请日：2005-10-21
申请人： Atsushi Hasegawa , Toshio Miyazawa
发明人： Atsushi Hasegawa , Toshio Miyazawa
IPC分类号： G02F1/1343
CPC分类号： G02F1/134363 , G02F1/133555
摘要： The present invention provides a liquid crystal display device which can reduce the difference in brightness between an image obtained from a reflection region and an image obtained from a transmission region. The liquid crystal display device includes a pixel electrode and a counter electrode in each pixel region on a liquid-crystal-side surface of one substrate out of respective substrates which are arranged to face each other with liquid crystal therebetween. The pixel region includes a transmission region and a reflection region. A gap between the pixel electrode and the counter electrode in the reflection region is set larger than the gap between the pixel electrode and the counter electrode in the transmission region.
摘要翻译：本发明提供一种能够减少从反射区域获得的图像与从透射区域获得的图像之间的亮度差异的液晶显示装置。液晶显示装置在各基板的一个基板的液晶侧表面的各像素区域中具有像素电极和对置电极，它们之间以液晶相互配置。像素区域包括透射区域和反射区域。反射区域中的像素电极和对置电极之间的间隙被设定为大于透射区域中的像素电极和对电极之间的间隙。

122. 发明申请

US20060085662A1 Method and apparatus for controlling the flow of data between two circuits by generating one or more phase shifted clock signals 失效
标题翻译：用于通过产生一个或多个相移时钟信号来控制两个电路之间的数据流的方法和装置
公开(公告)号：US20060085662A1
公开(公告)日：2006-04-20
申请号：US11292844
申请日：2005-12-01
申请人： Lew Chua-Eoan , Atsushi Hasegawa , Hsuan-Wen Wang
发明人： Lew Chua-Eoan , Atsushi Hasegawa , Hsuan-Wen Wang
IPC分类号： G06F1/04
CPC分类号： G06F5/06 , G06F1/06
摘要： An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.
摘要翻译：根据本发明的一个实施例的接口电路包括时钟信号，耦合到时钟信号线并产生参考时钟信号的第一锁相环，接收参考时钟信号的第二锁相环，产生一个或多个相移参考时钟信号，以及数据收发器电路，其耦合以接收所述时钟信号，所述参考时钟信号或所述相移基准时钟信号中的至少一个，以控制所述相移参考时钟信号之间的数据流第一电路和第二电路。根据本发明的一个实施例的接口电路可以有利地用于控制CPU和外部存储器之间的数据流。

123. 发明授权

US07003686B2 Interface circuit 失效
公开(公告)号：US07003686B2
公开(公告)日：2006-02-21
申请号：US10152653
申请日：2002-05-20
申请人： Lew Chua-Eoan , Atsushi Hasegawa , Hsuan-Wen Wang
发明人： Lew Chua-Eoan , Atsushi Hasegawa , Hsuan-Wen Wang
IPC分类号： G06F1/04 , G06F1/06 , G06F1/08 , G06F1/10 , G06F1/12
CPC分类号： G06F5/06 , G06F1/06
摘要： An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

124. 发明授权

US06925264B2 Optical transmitter and optical transmitting apparatus using the same 失效
公开(公告)号：US06925264B2
公开(公告)日：2005-08-02
申请号：US10071100
申请日：2002-02-11
申请人： Shigeru Tokita , Atsushi Hasegawa , Takahiro Hamagishi
发明人： Shigeru Tokita , Atsushi Hasegawa , Takahiro Hamagishi
IPC分类号： H04B10/27 , H04B10/07 , H04B10/2507 , H04B10/272 , H04B10/293 , H04B10/54 , H04B10/564 , H04B10/572 , H04B10/04
CPC分类号： H04B10/504 , H04B10/564
摘要： An optical transmitter for use in an optical transmitting system based on PDS (Passive Double Star) technology, does not erroneously output an optical signal when the optical transmitter is powered on/off. The optical transmitter has a current source 1 for outputting a drive current having a magnitude corresponding to an input control signal, a Laser diode (LD) for generating an optical output signal based on the received drive current, a modulator 9 for controlling the supply and cutoff of the drive current to the Laser diode (LD), a source voltage detector 3 for monitoring a source voltage to detect whether the source voltage is lower than a predetermined voltage, and a switch circuit 4 for outputting a control signal to the current source 1 to stop the supply of the drive current when the source voltage is determined to be lower than the predetermined voltage.

125. 发明授权

US06744479B2 Active matrix display device 有权
标题翻译：主动矩阵显示装置
公开(公告)号：US06744479B2
公开(公告)日：2004-06-01
申请号：US09919916
申请日：2001-08-02
申请人： Atsushi Hasegawa
发明人： Atsushi Hasegawa
IPC分类号： G02F1136
CPC分类号： G02F1/13454 , G02F1/1368 , G02F2001/136295
摘要： An active matrix display device is provided a display area including a set of pixel regions each having a first thin-film transistor, and a driving circuit forming area located outside the display area and having second thin-film transistors. A gate electrode of the first thin-film transistor is made of a material different than a gate signal line and has a portion that is directly laid on or under the gate signal line to establish electrical connection. A gate electrode of each of the second thin-film transistors is made of a material different than a wiring layer or electrode to be connected to it and has a portion that is directly laid on or under the wiring layer or electrode to establish electrical connection. The gate electrode of the first thin-film transistor is made of the same material as that of each of the second thin-film transistors. The gate signal line is made of the same material as the wiring layer or electrode.
摘要翻译：提供了一种有源矩阵显示装置，该显示区域包括一组各具有第一薄膜晶体管的像素区域，以及位于显示区域外部并具有第二薄膜晶体管的驱动电路形成区域。第一薄膜晶体管的栅极由与栅极信号线不同的材料制成，并且具有直接放置在栅极信号线上或下方的部分以建立电连接。每个第二薄膜晶体管的栅极由与要连接的布线层或电极不同的材料制成，并且具有直接放置在布线层或电极下方的部分以建立电连接。第一薄膜晶体管的栅电极由与第二薄膜晶体管中的每一个相同的材料制成。栅极信号线由与布线层或电极相同的材料制成。

126. 发明授权

US06698220B2 Automotive air conditioning system 有权
标题翻译：汽车空调系统
公开(公告)号：US06698220B2
公开(公告)日：2004-03-02
申请号：US10374195
申请日：2003-02-26
申请人： Tsuyoshi Yoneno , Atsushi Hasegawa , Yukihiro Hirose , Hiroshi Kamiya
发明人： Tsuyoshi Yoneno , Atsushi Hasegawa , Yukihiro Hirose , Hiroshi Kamiya
IPC分类号： F25B3904
CPC分类号： B60H1/3227 , B60H1/00371 , B60H2001/00235
摘要： In an automotive air conditioning system according to the present invention, a thin condenser 2 of a condensing unit portion 10 installed on a flat roof of a vehicle such as a bus is provided in such a manner as to be inclined downwardly from the front toward the rear of the vehicle, condenser fans 4 are provided directly above the condenser, and an air inlet 51 to the condenser is disposed in front of the condenser whereas air outlets 52 are disposed above the condenser.
摘要翻译：在根据本发明的汽车空调系统中，安装在诸如总线的车辆的平屋顶上的冷凝单元部分10的薄冷凝器2设置成从前向前倾斜向下倾斜车辆的后部，冷凝器风扇4直接设置在冷凝器的上方，并且冷凝器的空气入口51设置在冷凝器的前面，而空气出口52设置在冷凝器的上方。

127. 发明授权

US06279063B1 Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller 有权
标题翻译：具有至少第一和第二微型计算机的微机系统，每个微型计算机均可在主模式和从属模式下操作，具有可配置的总线访问控制终端和总线使用优先级控制器
公开(公告)号：US06279063B1
公开(公告)日：2001-08-21
申请号：US09467087
申请日：1999-12-10
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1300
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

128. 发明授权

US06223265B1 Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal 有权
标题翻译：单片机同步控制外部同步存储器，响应存储器时钟信号和时钟使能信号
公开(公告)号：US06223265B1
公开(公告)日：2001-04-24
申请号：US09192093
申请日：1998-11-13
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1200
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

129. 发明授权

US06212620B1 Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals 有权
标题翻译：单片机可在主从模式下工作，并具有可配置的总线控制端子
公开(公告)号：US06212620B1
公开(公告)日：2001-04-03
申请号：US09191313
申请日：1998-11-13
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1500
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

130. 发明授权

US5809274A Purge control for ON-chip cache memory 失效
标题翻译：片上高速缓存的清除控制
公开(公告)号：US5809274A
公开(公告)日：1998-09-15
申请号：US886464
申请日：1997-07-01
申请人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
发明人： Tadahiko Nishimukai , Atsushi Hasegawa , Kunio Uchiyama , Ikuya Kawasaki , Makoto Hanawa
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译：用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。控制器还具有要执行的指令作为输出。指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。

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