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121. 发明申请

US20090159954A1 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 有权
公开(公告)号：US20090159954A1
公开(公告)日：2009-06-25
申请号：US12359481
申请日：2009-01-26
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

122. 发明申请

US20090052015A1 METHOD FOR ACQUIRING SPECTRUM SHAPE OF A GAIN FLATTENING FILTER IN AN OPTICAL AMPLIFIER 失效
标题翻译：在光放大器中获取增益滤光片的光谱形状的方法
公开(公告)号：US20090052015A1
公开(公告)日：2009-02-26
申请号：US12195864
申请日：2008-08-21
申请人： Zhigang Wang , Aihua Yu
发明人： Zhigang Wang , Aihua Yu
IPC分类号： H01S3/00
CPC分类号： H01S3/06754 , H01S3/0014 , H01S3/1616 , H01S2301/04
摘要： A method for acquiring spectrum shape of a gain flattening filter of a doped optical fiber amplifier comprises the steps of: measuring spectrum shapes at two gain point (H, L) of the doped optical fiber with invariable fiber length respectively; and acquiring various gain spectrums of the doped optical fiber with various fiber length and various population inversion level according to an expression: ErGain(λ,x,L′)=[ErLGain(λ)+[ErHGain(λ)−ErLGain(λ)]*x]*L′, Wherein Gain(λ) refers to the spectral function of gain, x is Δ′inv/Δinv which refers to change of population inversion level, and L′ is set as proportion of doped fiber length. Gain spectrums of the doped optical fiber with various fiber length can be acquired by measuring spectrum shapes at two gain point (H, L) of the doped optical fiber in invariable fiber length and applying change rule of gain spectrum of the doped optical fiber in different population inversion level, which improves the flexibility for design of amplifier.
摘要翻译：一种用于获取掺杂光纤放大器的增益平坦滤波器的光谱形状的方法，包括以下步骤：分别测量具有不变光纤长度的掺杂光纤的两个增益点（H，L）处的光谱形状; 并且根据以下表达式获取具有各种光纤长度和各种总体反转电平的掺杂光纤的各种增益光谱：<？in-line-formula description =“In-line Formulas”end =“lead”？> ErGain（λ， x，L'）= [ErLGain（lambda）+ [ErHGain（lambda）-ErLGain（lambda）] * x] * L'，<？in-line-formula description =“In-line Formulas”end =“tail” ？>其中增益（lambda）是指增益的光谱函数，x是Delta'inv / Deltainv，其指的是群体反转级别的变化，L'被设置为掺杂光纤长度的比例。通过以不变的光纤长度测量掺杂光纤的两个增益点（H，L）处的光谱形状，并将掺杂光纤的增益光谱的变化规则应用于不同的光纤中，可以获得具有各种光纤长度的掺杂光纤的增益谱人口反演水平提高了放大器设计的灵活性。

123. 发明授权

US07418683B1 Constraint assistant for circuit design 有权
标题翻译：电路设计约束助手
公开(公告)号：US07418683B1
公开(公告)日：2008-08-26
申请号：US11233809
申请日：2005-09-21
申请人： Jean-Daniel Sonnard , Zhigang Wang , Hemanth Sampath
发明人： Jean-Daniel Sonnard , Zhigang Wang , Hemanth Sampath
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/74
摘要： A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types requiring special IC layout constraints. Subcircuit types are identified on the basis of netlist examination, as well as cues from the layout of the circuit schematic.
摘要翻译：一种用于设计IC布局的计算机辅助设计工具和方法，其通过基于需要特殊IC布局约束的子电路类型的电路原理图的自动识别来推荐子电路布局约束。基于网表检查的子电路类型，以及电路原理图布局的线索。

124. 发明申请

US20070215935A1 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 失效
标题翻译：非易失性双向晶体管可编程逻辑单元和阵列布局
公开(公告)号：US20070215935A1
公开(公告)日：2007-09-20
申请号：US11750650
申请日：2007-05-18
申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
发明人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , Zhigang Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

125. 发明申请

US20060023511A1 Flash memory unit and method of programming a flash memory device 有权
标题翻译：闪存单元和闪存设备编程方法
公开(公告)号：US20060023511A1
公开(公告)日：2006-02-02
申请号：US10909693
申请日：2004-08-02
申请人： Zhigang Wang , Nian Yang , Zhizheng Liu
发明人： Zhigang Wang , Nian Yang , Zhizheng Liu
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/12
摘要： Disclosed are a flash memory unit and a method of programming a flash memory device. The method of programming can include applying respective programming voltages to a control gate and a drain of the memory device. A source bias potential can be applied to a source of the memory device. The application of the source bias potential can be controlled with the selective application of one of the programming voltages to a source bias switching device.
摘要翻译：公开了一种闪速存储器单元和一种对闪速存储器件进行编程的方法。编程的方法可以包括将相应的编程电压施加到存储器件的控制栅极和漏极。源极偏置电位可以应用于存储器件的源极。可以通过选择性地将一个编程电压施加到源极偏置开关器件来控制源极偏置电位的应用。

126. 发明授权

US06987696B1 Method of improving erase voltage distribution for a flash memory array having dummy wordlines 有权
标题翻译：提高具有虚拟字线的闪存阵列的擦除电压分布的方法
公开(公告)号：US06987696B1
公开(公告)日：2006-01-17
申请号：US10885268
申请日：2004-07-06
申请人： Zhigang Wang , Nian Yang , Shenqing Fang
发明人： Zhigang Wang , Nian Yang , Shenqing Fang
IPC分类号： G11C16/00
CPC分类号： G11C16/16 , G11C16/0491 , H01L27/115
摘要： Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines.
摘要翻译：公开了一种用于擦除具有多个操作字线的闪速存储器阵列的存储器件以及与操作字线的末端相邻的至少一个伪字线的技术。擦除存储器件可以包括将栅极电压施加到字线并将偏置电压施加到伪字线。在一种布置中，在伪字线和操作字线的末端之间建立电连接。

127. 发明授权

US06963506B1 Circuit and technique for accurately sensing low voltage flash memory devices 有权
标题翻译：用于精确检测低压闪存器件的电路和技术
公开(公告)号：US06963506B1
公开(公告)日：2005-11-08
申请号：US10679179
申请日：2003-10-03
申请人： Zhigang Wang , Nian Yang , Yue-Song He
发明人： Zhigang Wang , Nian Yang , Yue-Song He
IPC分类号： G11C16/06 , G11C16/26 , G11C16/30
CPC分类号： G11C16/30 , G11C16/26
摘要： An exemplary sensing circuit for sensing the current drawn by a target memory cell comprises a first transistor connected across a first node and a second node, a load connected across the second node and a third node, and a voltage boosting circuit coupled to a supply voltage, wherein the voltage boosting circuit supplies a voltage at the third node which is greater than the supply voltage.
摘要翻译：用于感测由目标存储器单元汲取的电流的示例性感测电路包括跨越第一节点和第二节点连接的第一晶体管，跨过第二节点连接的负载和第三节点，以及耦合到电源电压的升压电路，其中所述升压电路在所述第三节点处提供大于所述电源电压的电压。

128. 发明申请

US20050230272A1 Porous biosensing device 审中-公开
标题翻译：多孔生物传感器
公开(公告)号：US20050230272A1
公开(公告)日：2005-10-20
申请号：US11035431
申请日：2005-01-14
申请人： Gil Lee , Jin-Won Park , Zhigang Wang
发明人： Gil Lee , Jin-Won Park , Zhigang Wang
IPC分类号： G01N27/26 , G01N33/00 , G01N33/543 , G01N33/68
CPC分类号： B01L3/5027 , B01L3/50853 , B01L3/50857 , B01L2300/0636 , B01L2300/0819 , B01L2300/0864 , B01L2400/0406 , G01N33/54366 , G01N33/5438 , G01N33/6872
摘要： This invention relates to the biosensor devices, their fabrication and use. The biosensor devices comprise a substrate supporting an array of microwells where each microwell can contain a biocompatible fluid and a membrane having a membrane protein of interest. In use the microwells can be addressable to detect and analyze a variety of analytes.
摘要翻译：本发明涉及生物传感器装置及其制造和使用。生物传感器装置包括支撑微孔阵列的基底，其中每个微孔可包含生物相容性流体和具有感兴趣的膜蛋白的膜。在使用中，微孔可以寻址以检测和分析各种分析物。

129. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

130. 发明授权

US06859748B1 Test structure for measuring effect of trench isolation on oxide in a memory device 有权
标题翻译：沟槽隔离对存储器件中氧化物的影响的测试结构
公开(公告)号：US06859748B1
公开(公告)日：2005-02-22
申请号：US10190420
申请日：2002-07-03
申请人： Nian Yang , Zhigang Wang , Tien-Chun Yang
发明人： Nian Yang , Zhigang Wang , Tien-Chun Yang
IPC分类号： H01L23/544 , G01R27/29 , G01S31/00
CPC分类号： H01L22/34
摘要： An apparatus for measuring effects of isolation processes (280) on an oxide layer (286) in a memory device (255) is described. In one embodiment, the apparatus comprises a structure (110) comprised of an array (110c) of memory devices (255). A testing unit (120) is coupled with the structure (110). The testing unit (120) is for performing various electrical tests on the array (110c) of memory devices (255). The testing unit (120) is also for providing data regarding each memory device (255) in the array (110c) of memory devices (255). An analyzer (120) is coupled with the structure (110) for analyzing results of the various electrical tests. This determines the condition of the oxide layer (286) of each memory device (255) in the array of memory devices (110c).
摘要翻译：描述了用于测量隔离过程（280）对存储器件（255）中的氧化物层（286）的影响的装置。在一个实施例中，该装置包括由存储器件（255）的阵列（110c）组成的结构（110）。测试单元（120）与结构（110）耦合。测试单元（120）用于在存储器件（255）的阵列（110c）上执行各种电测试。测试单元（120）还用于提供关于存储器件（255）的阵列（110c）中的每个存储器件（255）的数据。分析器（120）与结构（110）耦合，用于分析各种电气测试的结果。这决定了存储器件阵列（110c）中每个存储器件（255）的氧化物层（286）的状态。

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