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111. 发明专利

JP2004536334A Method and system for generating a pseudo comfort noise without silence insertion descriptor packet 审中-公开
公开(公告)号：JP2004536334A
公开(公告)日：2004-12-02
申请号：JP2003504387
申请日：2002-06-12
申请人：グローブスパンヴィラタ、インコーポレイテッドGlobespan Virata,Inc.
发明人：エスナヤック、ヴァスデヴ , ランドマー、マシュー , ワン、デイヴィッド
IPC分类号： G10L11/02 , G10L19/00 , G10L19/08 , H03B29/00 , H03G5/00 , H03H7/30 , H03H7/40 , H03K5/159 , H04M1/00
CPC分类号： H03G5/005 , G10L19/012 , G10L19/083 , G10L25/78 , G10L2021/02168 , G10L2025/783 , H03B29/00
摘要：本発明に係る方法とシステムは、音声の情報内容と音声とノイズ間の音声終了部分を使用して、デコーダ側で快適ノイズを生成する。ノイズへの適用は擬似ノイズのスペクトルを類推する種々のアルゴリズムを用いて行う。本発明の実施例によれば、適用されるアルゴリズムは、ブロックベースのアルゴリズムではなく、時間に適用されたものが実行され、これにより音声ブロック中に不自然な人口ノイズが繰り返して生成されるのを防止する。本発明の方法とシステムは、スペクトル情報を含む無音挿入記述子が存在しないときに快適ノイズを生成し、それにより通信バンド幅を節約し、かつ実際のノイズのスペクトルを反映した快適ノイズを生成する。

112. 发明专利

JP2001156551A METHOD FOR CANCELING SIGNAL AND ITS SYSTEM 失效
公开(公告)号：JP2001156551A
公开(公告)日：2001-06-08
申请号：JP34128599
申请日：1999-11-30
申请人： FUJITSU LTD
发明人： MIYAMOTO HIROMI , NAKANO YOSHIAKI , ABENO ICHIRO
IPC分类号： H03F1/32 , H03H11/04 , H03H11/22 , H03K5/159
摘要： PROBLEM TO BE SOLVED: To provide a method for canceling signals and its system that can quickly and reliably (stably) cancel an input signal. SOLUTION: The input signal is distributed into 1st and 2nd signals A, B, the 2nd signal B is distributed into 1st and 2nd sub signals B0, B90 that are orthogonal to each other, the amplitude of each of them is adjusted and they are recombined again as a 3rd signal B (B'), which is used to cancel the 1st signal A (A'). The amplitude of the orthogonal sub signals B0, B90 can independently be adjusted and the 3rd signal B (B') resulting from recombining the sub signals B0, B90 after the adjustment can be a cancellation signal with an optional phase and amplitude over 1st - 4th quadrants of the vector plane.

113. 发明专利

JPH11205197A DEVICE AND METHOD FOR REDUCING NUMBER OF ERROR SIGNAL BIT 失效
公开(公告)号：JPH11205197A
公开(公告)日：1999-07-30
申请号：JP30139798
申请日：1998-10-22
申请人： TEXAS INSTRUMENTS INC
发明人： RICHARD X GU , TRAN HIEP V
IPC分类号： H03H21/00 , H03K5/159 , H04B3/06 , H04B3/23 , H04L25/03
摘要： PROBLEM TO BE SOLVED: To reduce the constitution of a filter unit by reducing the number of bits for indicating error signals inside a transceiver unit provided with an adaptive equalizer filter unit. SOLUTION: This device 30 replaces the plural most significant signal bits e1 -e4 of input error signals with a single bit e'1 through an AND gate 42, an OR gate 41 and a switch unit 43 and transfers a code signal bit e0 and low-order signal bits e5 -e7 as an output code signal bit e'0 and output error signals e'2 -e'4 without changing them. Also, the control terminal of the switch unit 43 is connected to the code signal bit e0 . Because of the reduction of the number of the signal bits, the number of the constituting elements of a multiplication unit inside an adaptive filter unit is reduced. The result of the reduction does not affect the balance value of the error signals, however, increases the time of reaching the balance value.

114. 发明专利

JP2693874B2 失效
公开(公告)号：JP2693874B2
公开(公告)日：1997-12-24
申请号：JP5202491
申请日：1991-03-18
IPC分类号： H03K17/14 , G05F3/26 , H03K5/04 , H03K5/159 , H03K17/28

115. 发明专利

JPH06209286A CIRCUIT FOR INCREASING DYNAMIC RANGE OF TRANSMISSION CHANNEL FOR WIDEBAND TRANSIENT ANALOG SIGNAL 失效
公开(公告)号：JPH06209286A
公开(公告)日：1994-07-26
申请号：JP35623492
申请日：1992-12-21
申请人： THOMSON CSF
发明人： GURUGOWAARU YUMIYURIAN
IPC分类号： H04B10/02 , H03K5/06 , H03K5/159 , H04B1/62
摘要： PURPOSE: To provide a circuit which extends the dynamic range of a wide band transient analog signal. CONSTITUTION: The dynamic range extending circuit includes an amplife 2 and following direct channel Vo1 and delay attenuation channels. A first delay attenuation channel Vo2 of delay attenuation channels includes an attenuator 2 having an extent of attenuation K1 and a delay line LRe 1 having an extent of delay equal to a leading edge period T1 of the transient signal, and the other delay attenuation channel Vo3 is connected to the output of the preceding channel and includes an attenuator and a delay line LRe 2 having an extent of delay T1 . A multiplexer 4 controlled by a circuit 5 performs time division multiplexing of leading edges of transient signals having extents of attenuation K1, K2....

116. 发明专利

JPH05110388A SYNCHRONIZING CLOCK GENERATING CIRCUIT, DELAY PULSE GENERATING CIRCUIT USING THE SAME CL0CK GENERATING CIRCUIT AND LATCH CIRCUIT USED FOR THE SAID PULSE GENERATING CIRCUIT 失效
公开(公告)号：JPH05110388A
公开(公告)日：1993-04-30
申请号：JP30774291
申请日：1991-11-22
申请人： MITSUBISHI ELECTRIC CORP
发明人： HATANAKA MAKOTO , MIYAZAKI YUKIO
IPC分类号： H03K3/037 , G11C11/4076 , H03K5/13 , H03K5/133 , H03K5/159
摘要： PURPOSE:To generate a synchronizing clock without the use of a high frequency clock. CONSTITUTION:Inverting delay clocks S101a-108a and noninverting delay clocks S101b-S108b are generated by inverting and delaying a reference clock S1 by using inverting delay elements 101a-108b sequentially, and data given at the data input terminal D of the D flipflops 200-208 are outputted at the trailing of the reference clock S1 and the noninverting delay clocks S101b-S1O8b. The output of the adjacent D flip-flops 200-208 resulting from being compared by NAND circuits 300-308 are given to the data input terminal D and one of the inverting delay clocks S101a-108a is selected by the output of the NAND circuits 300-308 and it is further inverted to output a synchronizing clock. The synchronizing clock with high accuracy is obtained without occurrence of noise.

117. 发明专利

JPH0220022B2 失效
公开(公告)号：JPH0220022B2
公开(公告)日：1990-05-07
申请号：JP50004781
申请日：1980-10-20
申请人： UNISYS CORP
发明人： UTSUDOWAADO TOMASU AARU
IPC分类号： H03K5/159 , G11B20/14 , H04L7/00 , H04L7/02 , H04L25/49

118. 发明专利

JPS6347685A PHOTOELECTRIC DESTANCE MEASURING DEVICE BY PRINCIPLE OF TRANSMISSION-TIME MEASUREMENT 失效
公开(公告)号：JPS6347685A
公开(公告)日：1988-02-29
申请号：JP19927387
申请日：1987-08-11
申请人： ZELLWEGER USTER AG
发明人： JIRUBUIO MIRA , RUUDORUFU SHIYUBUARUTE
IPC分类号： G01S17/10 , G04F10/00 , H03K5/1536 , H03K5/159

119. 实用新型

JPS59119649U JPS59119649U - 失效
公开(公告)号：JPS59119649U
公开(公告)日：1984-08-13
申请号：JP1357083
申请日：1983-02-01
IPC分类号： H04B1/10 , H03H11/26 , H03K5/159

120. 发明专利

JPS59103392A Pulse form shaping circuit 失效
标题翻译：脉冲形状电路
公开(公告)号：JPS59103392A
公开(公告)日：1984-06-14
申请号：JP21322982
申请日：1982-12-04
申请人： Tdk Corp , Shuntaro Watabe
发明人： WATABE SHIYUNTAROU , SATOU HIROSHI , ONO KENJI
IPC分类号： B23K26/00 , H01G4/35 , H01S3/097 , H03K5/159
CPC分类号： H03K5/159
摘要： PURPOSE:To realize a circuit with large current and long pulse by a method wherein cylindrical dielectric ceramics respectively forming electrodes along internal and external periphery are provided to make both ends of the dielectric ceramics in the axial direction the pulse input and output terminals. CONSTITUTION:An internal periphery electrode 2 and an external periphery electrode 3 are respectively formed along the internal and external periphery of a cylindrical dielectric ceramics 1 as a pulse form shaping circuit. This pulse form shaping circuit is operated assuming the gap between electrodes 2 and 3 at an end A to be a pulse input terminal and the gap between electrodes 2 and 3 at the end B to be a pulse output terminal. In such a constitution, the impedance between the input terminal A and the output terminal B may be provided with a low value of 3OMEGA. Moreover this value may be reduced in reverse proportion to the parallel connection numbers thereof by means of connecting the pulse form shaping circuit in parallel in this constitution. Through these procedures, a rectangular wave pulse with fast rising high voltage and current for extremely low impedance load may be impressed for relatively long time.
摘要翻译：目的：通过一种方法来实现具有大电流和长脉冲的电路，其中设置分别沿内部和外部形成电极的圆柱形电介质陶瓷，以使电介质陶瓷的轴向两端的脉冲输入和输出端子。构成：作为脉冲形状整形电路，分别沿着圆筒形电介质陶瓷1的内周和外周分别形成内周电极2和外周电极3。该脉冲形状整形电路假定端部A处的电极2和3之间的间隙为脉冲输入端子，端部B的电极2和3之间的间隙为脉冲输出端子即可工作。在这种结构中，输入端子A和输出端子B之间的阻抗可以被设置为低的3OMEGA值。此外，该值可以通过在该结构中并联连接脉冲形状整形电路而与其并联连接数成反比地减小。通过这些程序，具有快速上升的高电压和电流的极低阻抗负载的矩形波脉冲可能会在相当长的时间内被印象。

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