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111. 发明申请

US20020105854A1 Apparatus for recognizing chip identification and semiconductor device comprising the apparatus 失效
标题翻译：用于识别芯片识别的装置和包括该装置的半导体装置
公开(公告)号：US20020105854A1
公开(公告)日：2002-08-08
申请号：US10055209
申请日：2002-01-23
发明人： Boo-yung Huh , Won-chul Kim
IPC分类号： G11C005/00
CPC分类号： G11C7/20 , G11C17/143 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/12 , G11C2029/4402 , H01L23/57 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an apparatus is provided for recognizing chip identification capable of minimizing the number of pads. The apparatus for recognizing chip identification comprises a counter circuit for counting a clock signal in response to a reset signal and decoding the counted clock signal to produce at least one decoding signal; and a fuse circuit comprising a plurality of fuse arrays, each fuse of the plurality of fuse arrays representing chip identification information, for outputting an output signal indicating whether each fuse of the plurality of fuse arrays is cut in response to the at least one decoding signal. The apparatus for recognizing chip identification minimizes the number of pads required for a semiconductor chip, occupies a small portion of a semiconductor device, and reads chip information in a package state of a semiconductor device.
摘要翻译：具有装置的半导体器件被提供用于识别能够最小化焊盘数量的芯片识别。用于识别芯片识别的装置包括用于响应于复位信号对时钟信号进行计数并解码计数的时钟信号以产生至少一个解码信号的计数器电路; 以及熔丝电路，其包括多个熔丝阵列，所述多个熔丝阵列中的每个熔丝表示芯片识别信息，用于输出指示所述多个熔丝阵列中的每个熔丝是否响应于所述至少一个解码信号被切断的输出信号。用于识别芯片识别的装置使半导体芯片所需的焊盘的数量最小化，占用半导体器件的一小部分，并且以半导体器件的封装状态读取芯片信息。

112. 发明申请

US20020105836A1 Method and device for storing and outputting data with a virtual channel 有权
标题翻译：用虚拟通道存储和输出数据的方法和设备
公开(公告)号：US20020105836A1
公开(公告)日：2002-08-08
申请号：US09932893
申请日：2001-08-20
发明人： Alexander Benedix
IPC分类号： G11C005/00
CPC分类号： G11C7/1006 , G11C7/1039 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A description is given of a method and a device for outputting data via a buffer memory. In which the data, which are intended to be output first from the buffer memory are selected. The selected data are written either to a predetermined area of the buffer memory and/or to the buffer memory temporally before the rest of the data and output.
摘要翻译：给出了通过缓冲存储器输出数据的方法和装置的描述。其中选择要从缓冲存储器首先输出的数据。选择的数据在数据的其余部分之前写入缓冲存储器的预定区域和/或暂时写入缓冲存储器并输出。

113. 发明申请

US20020097628A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20020097628A1
公开(公告)日：2002-07-25
申请号：US10107139
申请日：2002-03-28
发明人： Hiroki Fujisawa , Kazuhiko Kajigaya , Kenichi Fukui , Toshikazu Tachibana
IPC分类号： G11C005/00
CPC分类号： G11C5/147
摘要： In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
摘要翻译：在半导体集成电路中，对通过外部端子供给的电源电压进行动作的内部电压产生电路形成低电压和升压电压两者之一来操作内部电路，在电源电压上工作的第一内部电路通过外部端子供电或由内部电压产生电路形成的升压电压由具有适于电源电压或升压电压的大厚度的栅极绝缘膜的第一MOSFET和在低电平上工作的第二内部电路构成电压由具有适于低电压的小厚度的栅极绝缘膜的第二MOSFET构成。

114. 发明申请

US20020097617A1 Static semiconductor memory device capable of accurately detecting failure in standby mode 失效
标题翻译：能够准确检测待机模式下的故障的静态半导体存储器件
公开(公告)号：US20020097617A1
公开(公告)日：2002-07-25
申请号：US09912593
申请日：2001-07-26
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Minoru Senda , Shigeki Ohbayashi
IPC分类号： G11C005/00 , G11C007/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5004
摘要： A voltage supply circuit has a resistive element, a p-channel MOS transistor, and n-channel MOS transistors. The resistive element and the p-channel MOS transistor are connected in parallel between a power source node and a node. The n-channel MOS transistors are connected in series between the node and the ground node. The voltage supply circuit supplies a threshold voltage of the n-channel MOS transistor to the node connected to a cell Vcc line of a memory cell in response to a test mode signal TE of the H level, and supplies an external source voltage in response to a test mode signal of the L level. In such a manner, a memory cell having an abnormal current in a standby mode can be detected by an operation test.
摘要翻译：电压供给电路具有电阻元件，p沟道MOS晶体管和n沟道MOS晶体管。电阻元件和p沟道MOS晶体管并联连接在电源节点和节点之间。 n沟道MOS晶体管串联在节点和接地节点之间。电压供给电路响应于H电平的测试模式信号TE而将n沟道MOS晶体管的阈值电压提供给连接到存储单元的单元Vcc线的节点，并响应于 L级的测试模式信号。以这种方式，可以通过操作测试来检测具有待机模式中的异常电流的存储单元。

115. 发明申请

US20020095543A1 Storage medium, apparatus for creating recordation data therefor and apparatus for restoring recorded data 审中-公开
标题翻译：存储介质，用于创建记录数据的装置和用于恢复记录数据的装置
公开(公告)号：US20020095543A1
公开(公告)日：2002-07-18
申请号：US09892791
申请日：2001-06-28
申请人： PIONEER CORPORATION
发明人： Takehiko Shioda , Takuya Tanaka , Yukitaka Saito
IPC分类号： G11C005/00
CPC分类号： G11B20/00173 , G11B20/00086 , G11B20/10527
摘要： A storage medium (computer readable medium) for recording information data in a protective manner such that an easy data processing can hardly succeed correct reproduction of information such as music information. A machine for creating data to be recorded in the storage medium and a machine for restoring the recorded data. Incomplete information data which is obtained by omitting some data in complete information data adapted to provided complete information is recorded in the storage medium. The data creation machine separates the complete information data into the incomplete information data and complementary information data, and writes the incomplete information data into the storage medium. The data restoration machine includes a first storage unit for recording the incomplete information data, and a second storage unit for recording the complementary information data which is the data omitted from the complete information data. The data restoration machine combines the incomplete information data with the complementary information data to create the complete information data.
摘要翻译：用于以保护方式记录信息数据的存储介质（计算机可读介质），使得简单的数据处理几乎不能正确地再现诸如音乐信息的信息。用于创建要记录在存储介质中的数据的机器和用于恢复记录数据的机器。通过省略适于提供完整信息的完整信息数据中的一些数据而获得的不完整信息数据被记录在存储介质中。数据创建机将完整的信息数据分解为不完整的信息数据和补充信息数据，并将不完整的信息数据写入存储介质。数据恢复机包括用于记录不完整信息数据的第一存储单元和用于记录从完整信息数据中省略的数据的补充信息数据的第二存储单元。数据恢复机将不完整的信息数据与补充信息数据相结合，创建完整的信息数据。

116. 发明申请

US20020093868A1 Actively driven V REF for input buffer noise immunity 失效
标题翻译：积极驱动V REF的输入缓冲器噪声抗扰度
公开(公告)号：US20020093868A1
公开(公告)日：2002-07-18
申请号：US09759499
申请日：2001-01-12
发明人： Eric T. Stubbs , James E. Miller
IPC分类号： G11C005/00
CPC分类号： G11C5/147
摘要： A circuit and method for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memory device caused by power supply changes and noise occurring in the memory device by generating a constant voltage and good current drive from the external voltage source.
摘要翻译：公开了用于在存储器件中主动驱动参考电压的电路和方法。集成在存储器件中并耦合到外部电压源的电路基本上消除了由存储器件中发生的电源变化和噪声引起的存储器件参考电压的波动，通过从外部电压产生恒定电压和良好的电流驱动资源。

117. 发明申请

US20020093853A1 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US20020093853A1
公开(公告)日：2002-07-18
申请号：US10093800
申请日：2002-03-11
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Yoichi Hirata
IPC分类号： G11C005/00
CPC分类号： G06F8/66 , G06F9/328
摘要： To correct a software bug in a microcomputer for use in various electric apparatus having a mask ROM mounted therein without correcting the mask ROM. When there is a bug in a first data, a predetermined bit of a second data is arranged to be rewritten. Thereby, the software bug of the microcomputer is corrected.
摘要翻译：为了校正微型计算机中的软件错误，用于其中安装有掩模ROM的各种电气设备，而不修正掩模ROM。当第一数据存在错误时，第二数据的预定位被布置成被重写。由此，修正微型计算机的软件错误。

118. 发明申请

US20020085426A1 Apparatus for varying data input/output path in semiconductor memory device 失效
标题翻译：用于在半导体存储器件中改变数据输入/输出路径的装置
公开(公告)号：US20020085426A1
公开(公告)日：2002-07-04
申请号：US10028431
申请日：2001-12-28
发明人： Joo Sang Lee
IPC分类号： G11C005/00
CPC分类号： G11C7/1051 , G11C7/1045 , G11C7/1048
摘要： An apparatus for varying a data input/output path in a memory device, includes DBSAs amplifying a signal loaded on a data bus, fuse circuits producing output signals of specific levels respectively in accordance with whether or not fuses are cut, input multiplexers each of which selects either an external signal inputted through a corresponding pad or another external signal inputted through a pad next to the corresponding pad in accordance with the output signals of the fuse circuits, and applies the selected signal to a write driver, and data input/output parts including output multiplexers, each of the output multiplexers selecting a signal outputted from either a corresponding one of the DBSAs or one next to the corresponding DBSA in accordance with the output signals of the fuse circuits, and outputting the selected signal through a corresponding pad.
摘要翻译：一种用于改变存储装置中的数据输入/输出路径的装置，包括放大数据总线上加载的信号的DBS，根据是否切断保险丝分别产生特定电平的输出信号的熔丝电路，输入多路复用器根据熔丝电路的输出信号选择通过相应焊盘输入的外部信号或通过焊盘输入的另一外部信号，并将选择的信号施加到写入驱动器，以及数据输入/输出部分包括输出多路复用器，每个输出多路复用器根据熔丝电路的输出信号选择从相应的一个DBSA或相应的DBSA的一个输出的信号，并通过相应的衬垫输出所选择的信号。

119. 发明申请

US20020071318A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20020071318A1
公开(公告)日：2002-06-13
申请号：US10067902
申请日：2002-02-08
发明人： Hiroyuki Mizuno , Takao Watanabe , Mitsuru Hiraki , Hitoshi Tanaka
IPC分类号： G11C005/00
CPC分类号： G11C5/14 , G11C5/147
摘要： A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.
摘要翻译：一种半导体器件，具有提供有第一工作电压的第一电路块，提供有第二工作电压的第二电路块，用于响应于第一工作电压产生第三工作电压的电压产生电路，以及提供的第三电路块具有第三工作电压。优选地，产生第三工作电压，使得通过升压转换器将第一工作电压增加到第四工作电压，然后通过电压下变频器将第四工作电压降至第三工作电压。因此，即使在电源电压下降的情况下，即使使用相对波动的电压也能够内部稳定地工作的电源。

120. 发明申请

US20020067642A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20020067642A1
公开(公告)日：2002-06-06
申请号：US09962147
申请日：2001-09-26
申请人： FUJITSU LIMITED
发明人： Akira Kikutake , Shinichiro Shiratake , Kuninori Kawabata
IPC分类号： G11C005/00
CPC分类号： G11C7/18 , G11C5/025 , G11C5/063
摘要： Read amplifiers are arranged adjacent to each other near the center of an amplifier string, thereby shortening the distances of read data paths from sense amplifiers to the read amplifiers. This can suppress the delay of a read operation caused by the wiring resistance of a data bus line, to realize high-speed read and write operations by reducing the wiring load on data paths in data read and write.
摘要翻译：读取放大器在放大器串的中心附近彼此相邻地布置，从而缩短读取数据路径从读出放大器到读取放大器的距离。这可以抑制由数据总线的布线电阻引起的读取操作的延迟，通过减少数据读取和写入中的数据路径上的布线负载来实现高速读取和写入操作。

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