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111. 发明申请

WO2005013495A3 SPACE EFFICIENT LOW POWER CYCLIC A/D CONVERTER 审中-公开
标题翻译：空间高效低功耗循环A / D转换器
公开(公告)号：WO2005013495A3
公开(公告)日：2005-06-09
申请号：PCT/US2004022511
申请日：2004-07-15
申请人： FREESCALE SEMICONDUCTOR INC , ATRISS AHMAD H , ALLEN STEVEN P
发明人： ATRISS AHMAD H , ALLEN STEVEN P
IPC分类号： H03M1/06 , H03M1/34 , H03M1/40 , H04B20060101
CPC分类号： H03M1/0695 , H03M1/40
摘要： Methods and apparatus are provided for an analog converter (60). The apparatus comprises a first redundant signed digit (RSD) stage (62) and a configurable block (61). The configurable block (61) converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage (62). The first RSD stage (62) outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage (62) calculates a residue that is provided to the configurable block (61). The configurable block (61) is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block (61) is then converted back to a sample/hold circuit to start another conversion process.
摘要翻译：提供了用于模拟转换器（60）的方法和装置。该装置包括第一冗余有符号数字（RSD）级（62）和可配置块（61）。可配置模块（61）转换为采样/保持电路以采样单端模拟信号。然后对采样的信号进行缩放，转换成差分信号并提供给第一RSD级（62）。第一RSD级（62）输出对应于数字信号大小的比特值。在下一个半时钟周期中，第一RSD级（62）计算提供给可配置块（61）的余量。可配置块（61）被转换成第二冗余有符号数位级，并且生成与由第一RSD级提供的残留量相对应的比特值。第一和第二RSD级每半个时钟周期前后循环产生逻辑值，直到达到期望的位分辨率。然后可配置模块（61）被转换回采样/保持电路以开始另一个转换过程。

112. 发明申请

WO2004010586A2 SWITCHED-CURRENT ANALOGUE-TO-DIGITAL CONVERTER 审中-公开
标题翻译：开关电流模拟数字转换器
公开(公告)号：WO2004010586A2
公开(公告)日：2004-01-29
申请号：PCT/IB0303027
申请日：2003-07-08
申请人： KONINKL PHILIPS ELECTRONICS NV , HUGHES JOHN B
发明人： HUGHES JOHN B
IPC分类号： H03M1/44 , H03M1/06 , H03M1/00
CPC分类号： H03M1/0695 , H03M1/447
摘要： A current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit (120, 130, 135) samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit (140). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits (140, 140") may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (S
摘要翻译：电流模式模拟 - 数字转换器使用转换级，其使用两相时钟进行操作，并且需要在仅一个相位期间存在输入信号。采样和保持电路（120,130,135）在第一时钟相位期间对输入信号进行采样，并且在第二时钟相位期间，通过无反冲比较器电路从保持的输入电流的反射镜产生量化位值（140）。同样在第二时钟阶段期间，使用量化值和保持的输入电流的非镜像版本来生成残差。可选地，可以使用两个比较器电路（140,140“）来提供两级量化，使得由电流镜引入的误差能够通过冗余有符号数字算法来校正。转换级的两条管线（S

113. 发明公开

EP3090488A1 COMBINING A COARSE ADC AND A SAR ADC 有权
标题翻译：组合粗糙和ADC SAR ADC的
公开(公告)号：EP3090488A1
公开(公告)日：2016-11-09
申请号：EP14877496.1
申请日：2014-12-31
申请人： Texas Instruments Incorporated
发明人： NARAYAN, Subramanian, Jagdish , KANNAN, Anand
IPC分类号： H03M1/38
CPC分类号： H03M1/144 , H03M1/0604 , H03M1/0695 , H03M1/468
摘要： In described examples, a successive approximation register analog to digital converter (SAR ADC) receives an input voltage (102) and multiple reference voltages (105). The SARADC (100) includes a charge sharing DAC (110). The charge sharing DAC (110) includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector (116) is coupled to the charge sharing DAC (110). The zero crossing detector (116) generates a digital output ( 118). A coarse ADC ( 122) receives the input voltage ( 102) and generates a coarse output (124). A predefined offset is added to a residue of the coarse ADC (122). A successive approximation register (SAR) state machine (120) is coupled to the coarse ADC (122) and the zero crossing detector (116) and generates multiple control signals (126). The control signals (126) operate the charge sharing DAC (110) in a sampling mode, an error-correction mode and a conversion mode.

114. 发明公开

EP2760135A4 ANALOG/DIGITAL CONVERTER AND METHOD FOR CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS 审中-公开
标题翻译：模拟数字转换器和方法用于转换模拟信号的数字信号
公开(公告)号：EP2760135A4
公开(公告)日：2016-04-13
申请号：EP12833874
申请日：2012-09-06
申请人： JAPAN SCIENCE & TECH AGENCY
发明人： SAN HAO , MARUYAMA TSUBASA , HOTTA MASAO
IPC分类号： H03M1/06 , H03M1/10 , H03M1/40 , H03M1/44
CPC分类号： H03M1/14 , H03M1/0609 , H03M1/0692 , H03M1/0695 , H03M1/1014 , H03M1/1205 , H03M1/40 , H03M1/403 , H03M1/442

115. 发明公开

EP2966780A1 Analog-to-digital converter offset cancellation 审中-公开
标题翻译：模拟数字-Wandler-Offsetunterdrückung
公开(公告)号：EP2966780A1
公开(公告)日：2016-01-13
申请号：EP14306111.7
申请日：2014-07-07
申请人： STMicroelectronics International N.V.
发明人： Vaccariello, Laurent
IPC分类号： H03M1/06 , H03M1/40
CPC分类号： H03M1/0663 , H03M1/0682 , H03M1/0695 , H03M1/403
摘要： There is described a cyclic pipelined Analog-to-Digital Converter having an input (41) adapted to receive an analog voltage (V IN ) to be converted, and an output (42) adapted to deliver a n-bit digital value (N OUT ). The converter also comprises a core stage (40) comprising an Analog-to-Digital Conversion stage (50) to provide at least one bit value of the n-bit digital value at each one of a plurality of successive conversion steps performed in loop by the core stage (40). The core stage (40) further comprises a differential inputs-differential outputs amplifier (59). In order to cancel the offset of the stage (55, 58), the coupling of the amplifier inputs is inversed, i.e. the inputs are switched around, namely swapped, just after the first conversion step has been carried out. Simultaneously the differential outputs of the amplifier are similarly swapped.
摘要翻译：描述了具有适于接收要转换的模拟电压（V IN）的输入端（41）的循环流水线模数转换器和适于传送n位数字值（N OUT）的输出（42））。转换器还包括核心级（40），其包括模数转换级（50），以在循环中以循环执行的多个连续转换步骤中的每一个提供n位数字值的至少一个位值核心阶段（40）。核心级（40）还包括差分输入差分输出放大器（59）。为了消除级（55,58）的偏移，放大器输入的耦合被反转，即刚刚在执行第一转换步骤之后，输入被切换，即交换。同时，放大器的差分输出也同样交换。

116. 发明公开

EP2760135A1 ANALOG/DIGITAL CONVERTER AND METHOD FOR CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS 审中-公开
标题翻译：模拟数字万用表VERFAHREN ZUR UMWANDLUNG VON ANALOGEN SIGNALEN IN DIGITALE SIGNALE
公开(公告)号：EP2760135A1
公开(公告)日：2014-07-30
申请号：EP12833874.6
申请日：2012-09-06
申请人： Japan Science and Technology Agency
发明人： SAN, Hao , MARUYAMA, Tsubasa , HOTTA, Masao
IPC分类号： H03M1/14
CPC分类号： H03M1/14 , H03M1/0609 , H03M1/0692 , H03M1/0695 , H03M1/1014 , H03M1/1205 , H03M1/40 , H03M1/403 , H03M1/442
摘要： The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing. An A/D converter (1) of the invention, which is a cyclic type of analog/digital converter for converting an analog input signal to a digital signal having a predetermined resolution, comprises: a digital approximation unit (10) that includes a comparing unit (13) for comparing the magnitude of an input first analog signal with a threshold value to output a digital value indicating a result of the comparison and that also includes an MDAC unit (14) for amplifying the first analog signal to β-fold, where β is greater than one but smaller than two, and for executing a predetermined computation in accordance with the result of the comparison of the comparing unit to output a second analog signal; a multiplexer (20) that, if the MSB is to be computed, outputs the analog input signal and, otherwise, outputs the second analog signal as the first analog signal; a β estimating unit (30) that estimates the value of β; and a digital signal outputting unit (40) that sequentially takes in digital values outputted by the comparing unit and that outputs the taken-in digital values as the digital signal.
摘要翻译：本发明的目的是提供一种A / D转换器，其由于制造变化而显示出更少的故障。本发明的A / D转换器（1）是用于将模拟输入信号转换为具有预定分辨率的数字信号的循环型模拟/数字转换器，包括：数字近似单元（10），包括比较单元（13），用于将输入的第一模拟信号的幅度与阈值进行比较，以输出指示比较结果的数字值，并且还包括用于将第一模拟信号放大到二倍的MDAC单元（14）其中²大于1但小于2，并且用于根据比较单元的比较结果执行预定的计算以输出第二模拟信号; 多路复用器（20），如果要计算MSB，则输出模拟输入信号，否则输出第二模拟信号作为第一模拟信号; ²估计²的估计单位（30）; 以及数字信号输出单元（40），其顺序地取入由比较单元输出的数字值，并将所接收的数字值作为数字信号输出。

117. 发明公开

EP2587674A3 Multi-bit successive approximation ADC 审中-公开
标题翻译：多比特模拟 - 数字与逐次逼近转换器
公开(公告)号：EP2587674A3
公开(公告)日：2014-04-30
申请号：EP12189584.1
申请日：2012-10-23
申请人： Semtech Corporation
发明人： Nys, Olivier , Wong, Ark-Chew
IPC分类号： H03M1/14 , H03M1/46 , H03M1/06
CPC分类号： H03M1/144 , H03M1/0695 , H03M1/468
摘要： Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

118. 发明公开

EP2351225A1 PIPELINED ADC CALIBRATION 有权转让
标题翻译：根据传送带方法A / D转换器的校准
公开(公告)号：EP2351225A1
公开(公告)日：2011-08-03
申请号：EP09743923.6
申请日：2009-10-19
申请人： NXP B.V.
发明人： ERDMANN, Christophe , BIALLAIS, A.
IPC分类号： H03M1/10 , H03M5/22 , H03M1/06 , H03M1/16 , H03M1/80
CPC分类号： H03M1/1057 , H03M1/0695 , H03M1/164 , H03M1/804
摘要： A method of calibrating a pipelined analog to digital converter (400) having a plurality of DAC elements (410) and an additional calibration DAC element (420), in which a combination of positive, negative and zero reference voltages to the element under calibration and positive and negative reference voltages to the additional calibration DAC element to obtain four calibration states from which an error of the element under calibration is extracted by calculating an average of the difference between the four calibration states.

119. 发明授权

EP1638208B1 Switched-capacitor circuit and pipelined A/D converter 有权
标题翻译：电路开关电容和管线模拟数字转换器
公开(公告)号：EP1638208B1
公开(公告)日：2008-01-16
申请号：EP05251089.8
申请日：2005-02-24
申请人： FUJITSU LIMITED
发明人： Yoshioka, Masato, c/o Fujitsu Limited , Kudo, Masahiro, c/o Fujitsu Limited
IPC分类号： H03M1/12
CPC分类号： G11C27/026 , G11C27/024 , H03M1/0695 , H03M1/167 , H03M1/442

120. 发明授权

EP1182781B1 Multistage converter employing digital dither 有权
标题翻译：使用数字抖动信号的多级转换器
公开(公告)号：EP1182781B1
公开(公告)日：2006-10-04
申请号：EP01307008.1
申请日：2001-08-17
申请人： Agere Systems Guardian Corporation
发明人： Fetterman, Scott H. , Rich, David Arthur
IPC分类号： H03M1/06 , H03M1/44 , H03M1/16
CPC分类号： H03M1/0641 , H03M1/0695 , H03M1/167 , H03M1/442

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