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111. 发明授权

US06724670B2 Shared redundancy for memory having column addressing 有权
标题翻译：具有列寻址的存储器的共享冗余
公开(公告)号：US06724670B2
公开(公告)日：2004-04-20
申请号：US10277063
申请日：2002-10-21
申请人： William F. Jones , Wen Li
发明人： William F. Jones , Wen Li
IPC分类号： G11C700
CPC分类号： G11C29/812
摘要： A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.
摘要翻译：共享冗余预取方案，以提供减少数量的保险丝。 DDR SDRAM允许以各种突发长度进行脉冲串寻址。 DDR SDRAM通常实现LEFT和RIGHT段列寻址。在实现冗余存储器阵列的DDR SDRAM中，可以使用保险丝来提供对冗余列的访问。因为突发寻址可能以RIGHT段地址开始，所以可以在同一时钟周期访问两个不同的列。通过提供对LEFT和RIGHT段的低位执行单独的比较逻辑的比较方案，并将这些比特与用于LEFT和RIGHT段的公共保险丝组比较，冗余DDR SDRAM方案中的熔丝数可以是减少

112. 发明授权

US06665219B2 Method of reducing standby current during power down mode 失效
公开(公告)号：US06665219B2
公开(公告)日：2003-12-16
申请号：US10199130
申请日：2002-07-22
申请人： Wen Li , Mark R. Thomann , Daniel R. Loughmiller , Scott Schaefer
发明人： Wen Li , Mark R. Thomann , Daniel R. Loughmiller , Scott Schaefer
IPC分类号： G11C700
CPC分类号： G11C5/14
摘要： An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

113. 发明授权

US06624660B2 CMOS output driver for semiconductor device and related method for improving latch-up immunity in a CMOS output driver 有权
标题翻译：用于半导体器件的CMOS输出驱动器和用于提高CMOS输出驱动器中的闭锁抑制的相关方法
公开(公告)号：US06624660B2
公开(公告)日：2003-09-23
申请号：US10010820
申请日：2001-12-06
申请人： Wen Li , Michael D. Chaine , Manny Kin Ma
发明人： Wen Li , Michael D. Chaine , Manny Kin Ma
IPC分类号： H03K19094
CPC分类号： H03K19/00315
摘要： An output driver circuit for a semiconductor device. In one embodiment, the output driver is coupled to an output terminal of the semiconductor device and consists of an N-channel pull-down transistor and a P-channel pull-up transistor formed in an N-well in a P-type substrate. A tie-down region formed in the N-well is selectively coupled to a supply potential by means of a decoupling transistor, and during normal operation of the driver maintains the supply voltage bias of the N-well. An overdrive detection circuit is coupled to the output terminal. Upon detection of an overdrive condition on the output terminal, such as a voltage exceeding a predetermined maximum, or excessive current injected into the output terminal (or both), the overdrive detection circuit deasserts a control signal applied to the gate of the decoupling transistor, thereby decoupling the N-well from the supply potential. In one embodiment, the decoupling transistor is not coupled to the output terminal.
摘要翻译：一种用于半导体器件的输出驱动器电路。在一个实施例中，输出驱动器耦合到半导体器件的输出端子，并且由形成在P型衬底中的N阱中的N沟道下拉晶体管和P沟道上拉晶体管组成。形成在N阱中的结合区域通过去耦晶体管选择性地耦合到电源电位，并且在驱动器的正常操作期间维持N阱的电源电压偏置。过驱动检测电路耦合到输出端子。在检测出输出端子上的过驱动条件（例如超过预定最大值的电压）或注入输出端子（或两者）的过电流时，过驱动检测电路解除施加到去耦晶体管的栅极的控制信号，从而将N阱与电源电位分离。在一个实施例中，去耦晶体管不耦合到输出端。

114. 发明授权

US06532180B2 Write data masking for higher speed DRAMs 失效
标题翻译：为更高速的DRAM写入数据屏蔽
公开(公告)号：US06532180B2
公开(公告)日：2003-03-11
申请号：US09883957
申请日：2001-06-20
申请人： Kevin J. Ryan , Christopher K. Morzano , Wen Li
发明人： Kevin J. Ryan , Christopher K. Morzano , Wen Li
IPC分类号： G11C700
CPC分类号： G11C7/1078 , G11C7/1006 , G11C11/4087 , G11C11/4096
摘要： A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., ×16 or ×32.
摘要翻译：公开了一种用于掩蔽写入存储器件的数据的方法和装置，其减少了存储器件的有效写周期时间。列选择的触发被抢占，从而掩蔽要写入存储器件的数据。通过预先排除列选择，可以消除禁用写驱动程序所需的余量，从而减少有效的写周期。另外，通过将独立列选择与多字节宽的器件上的每个数据字节（例如x16或x32）相关联，可以在每个字节的基础上执行数据屏蔽。

115. 发明授权

US06480429B2 Shared redundancy for memory having column addressing 有权
标题翻译：具有列寻址的存储器的共享冗余
公开(公告)号：US06480429B2
公开(公告)日：2002-11-12
申请号：US09781808
申请日：2001-02-12
申请人： William F. Jones , Wen Li
发明人： William F. Jones , Wen Li
IPC分类号： G11C700
CPC分类号： G11C29/812
摘要： A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.
摘要翻译：共享冗余预取方案，以提供减少数量的保险丝。 DDR SDRAM允许以各种突发长度进行脉冲串寻址。 DDR SDRAM通常实现LEFT和RIGHT段列寻址。在实现冗余存储器阵列的DDR SDRAM中，可以使用保险丝来提供对冗余列的访问。因为突发寻址可能以RIGHT段地址开始，所以可以在同一时钟周期访问两个不同的列。通过提供对LEFT和RIGHT段的低位执行单独的比较逻辑的比较方案，并将这些比特与用于LEFT和RIGHT段的公共保险丝组比较，冗余DDR SDRAM方案中的熔丝数可以是减少

116. 发明授权

US06438060B1 Method of reducing standby current during power down mode 有权
标题翻译：降低待机电流的方法
公开(公告)号：US06438060B1
公开(公告)日：2002-08-20
申请号：US09780606
申请日：2001-02-12
申请人： Wen Li , Mark R. Thomann , Daniel R. Loughmiller , Scott Schaefer
发明人： Wen Li , Mark R. Thomann , Daniel R. Loughmiller , Scott Schaefer
IPC分类号： G11C700
CPC分类号： G11C5/14
摘要： An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.
摘要翻译：一种用于在断电模式操作期间通过中断延迟线的时钟转换来降低存储器集成电路的功耗的装置和方法。存储器集成电路可以包括延迟锁定环，其包括串联连接并且适于延迟自由运行时钟的信号的传播的多个延迟元件。当不需要延迟信号时，如在断电模式操作期间，防止自由运行的时钟信号到达延迟锁定环路。因此，延迟元件不切换，并且节省与延迟元件切换相关联的功率。

117. 发明授权

US5661428A Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit 失效
标题翻译：频率可调，零温度系数参考环形振荡器电路
公开(公告)号：US5661428A
公开(公告)日：1997-08-26
申请号：US631993
申请日：1996-04-15
申请人： Wen Li , Manny K. F. Ma
发明人： Wen Li , Manny K. F. Ma
IPC分类号： G05F3/24 , G05F3/26 , G05F3/08
CPC分类号： G05F3/262 , G05F3/242
摘要： A frequency adjustable, zero temperature coefficient referencing ring oscillator circuit includes a plurality of inverter stages each having a switching circuit that produces the oscillating output signal for the ring oscillator circuit and a control circuit that controls the switching circuit to establish the frequency of the output signal, the control circuit including field-effect transistors which are operated as output resistance controllable devices and which have their operating points, and thus their output resistances, established by a reference voltage that is produced by a precision reference voltage generating circuit so that the operating frequency of the ring oscillator circuit can be set by adjusting the value of the reference signals produced by the precision reference signal generating circuit and is maintained at the setpoint value because the precision reference voltage generating circuit operates independently of variations in temperature and/or the power supply voltage. The ring oscillator circuit is fabricated as an integrated circuit device and the operating frequency of the integrated circuit ring oscillator circuit can be adjusted after fabrication and passivation of the integrated circuit device.
摘要翻译：频率可调，零温度系数参考环形振荡器电路包括多个反相器级，每个反相器级具有产生环形振荡器电路的振荡输出信号的开关电路和控制开关电路以建立输出信号频率的控制电路所述控制电路包括作为输出电阻可控设备操作并具有其工作点的场效应晶体管，并且因此其输出电阻由由精密参考电压产生电路产生的参考电压建立，使得工作频率可以通过调整精密基准信号发生电路产生的参考信号的值来设置环形振荡器电路，并且由于精密基准电压产生电路独立于温度和/或电源的变化而运行，因此保持在设定值卷天气好环形振荡器电路被制造为集成电路器件，并且集成电路环形振荡器电路的工作频率可以在集成电路器件的制造和钝化之后被调整。

118. 发明申请

US20230079864A1 APPARATUS AND METHODOLOGY FOR AIMING POINT AND AIMING DEVICE 6DOF DETECTION USING IMAGE REGISTRATION 有权
公开(公告)号：US20230079864A1
公开(公告)日：2023-03-16
申请号：US17473297
申请日：2021-09-13
申请人： Wen Li , Ming Yang
发明人： Wen Li , Ming Yang
IPC分类号： G06T7/80 , G03B17/56 , G06T7/73
摘要： A system and a method for determining aiming point and/or six degrees of freedom of an aiming device. The system include the aiming device, a camera mounted thereon, and a computing device. The aiming point is an intersection between a line of interest (LOI) of the aiming device and surface of an aimed object. A parallel auxiliary line (PAL) is a line starting from the camera and parallel to the LOI. The PAL is a point (PAL-T) in a template image captured by the first camera. The computing device is configured to: provide a reference image; map the template image to the reference image; project the PAL-T to the reference image using the mapping relation to obtain a reference point (PAL-R); determine 3D coordinates PAL-3D of the PAL-R; and determine 3D coordinates of the aiming point based on the PAL-3D and a relationship between the LOI and the PAL.

119. 发明授权

US09096747B2 Isotactic polypropylene nucleation 有权
标题翻译：全同立构聚丙烯成核
公开(公告)号：US09096747B2
公开(公告)日：2015-08-04
申请号：US12013183
申请日：2008-01-11
申请人： Derek Thurman , Sudhin Datta , Wen Li , Charles L. Sims
发明人： Derek Thurman , Sudhin Datta , Wen Li , Charles L. Sims
IPC分类号： C08L23/04 , C08L23/10 , C08L23/14 , C08L23/12
CPC分类号： C08L23/10 , C08L23/12 , C08L23/142 , C08L2205/02 , C08L2666/06
摘要： Low molecular weight semicrystalline propylene-alpha olefin copolymers containing propylene crystallinity are used as a nucleating agent in crystalline polypropylene and polypropylene copolymers. The nucleating copolymers are propylene-alpha olefin copolymers having a percent crystallinity of 5-75%, a melting point of 45° C.-105° C., and an MFR between 300 and 5000 g/10 min. Nucleated polypropylene compositions comprise a nucleating amount of the copolymer blended in a matrix of polypropylene homopolymer, or 0.01 to 9 wt % α-olefin copolymer, having a melting point greater than 110° C. The nucleating copolymer improves processing time with little or no effect on the crystallinity-associated characteristics of the matrix. The invention also provides methods of crystallizing polypropylene with the nucleating agent and of forming articles with the composition, and also provides articles formed from the composition and/or by the method.
摘要翻译：含有丙烯结晶度的低分子量半结晶丙烯-α烯烃共聚物用作结晶聚丙烯和聚丙烯共聚物中的成核剂。成核共聚物是结晶度为5-75％，熔点为45℃-105℃，MFR为300-5000g / 10min的丙烯-α-烯烃共聚物。成核聚丙烯组合物包含在聚丙烯均聚物基质中混合的成核量的共聚物，或熔点大于110℃的0.01至9重量％的α-烯烃共聚物。成核共聚物改善处理时间，几乎没有或没有效果关于基质的结晶性相关特征。本发明还提供了使聚丙烯与成核剂结晶并形成具有该组合物的制品的方法，还提供了由该组合物和/或该方法形成的制品。

120. 发明申请

US20140303579A1 Fluid-Storing, Filtering, and Gas-Discharging Apparatus and Hematoma Evacuator Based on the Liquid-Stroing, Filtering, and Air-Discharging Apparatus 有权
标题翻译：流体储存，过滤和排气装置和基于液体驱动，过滤和排气装置的血液净化装置
公开(公告)号：US20140303579A1
公开(公告)日：2014-10-09
申请号：US14354927
申请日：2012-10-09
申请人： Guangcheng Li , Na Lu , Wen Li , Wenyong Zhang
发明人： Guangcheng Li , Na Lu , Wen Li , Wenyong Zhang
IPC分类号： A61M1/34 , A61M1/00
CPC分类号： A61M1/34 , A61M1/0056 , A61M1/3626 , A61M1/3627 , A61M2205/3331 , A61M2205/7545 , B01D19/00 , B01D19/0031 , F04C2270/041
摘要： A fluid-storing, filtering, and gas-discharging apparatus (2) comprising a fluid holder (21), a gas detector (23), and a filter (22). The fluid holder (21) has a protruding apex structure and comprises a fluid inlet and a fluid outlet. A gas-discharging pipe in communication with the outside is arranged on the protruding apex of the fluid holder (21). The gas detector (23) is arranged on the gas-discharging pipe. The filter (22) is fixed within the fluid holder (21) and is connected to the fluid outlet. The fluid-storing, filtering, and gas-discharging apparatus (2) uses the fluid holder (21) and the filter (22) to implement the storage and filtration of a working fluid, while at the same time, the fluid holder (21) having the protruding apex structure ensures complete discharging of gases mixed in the working fluid, thus achieves the goals of fluid storage, filtration, and gas discharge, and provides great reliability.
摘要翻译：包括流体保持器（21），气体检测器（23）和过滤器（22）的流体储存，过滤和气体排放装置（2）。流体保持器（21）具有突出的顶点结构，并且包括流体入口和流体出口。与流体保持器（21）的突出的顶点配置有与外部连通的排气管。气体检测器（23）布置在气体排出管上。过滤器（22）固定在流体保持器（21）内并连接到流体出口。流体储存，过滤和排气装置（2）使用流体保持器（21）和过滤器（22）来实现工作流体的储存和过滤，同时流体保持器（21））具有突出的顶点结构，确保了混合在工作流体中的气体的完全排出，从而实现了流体储存，过滤和排气的目的，并且提供了极高的可靠性。

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