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111. 发明申请

US20080077833A1 METHOD AND STRUCTURE FOR PICOSECOND-IMAGING-CIRCUIT-ANALYSIS BASED BUILT-IN-SELF-TEST DIAGNOSTIC 失效
标题翻译：基于PICOSECOND-IMAGING-CIRCUIT-ANALYSIS的内置自检测试方法和结构
公开(公告)号：US20080077833A1
公开(公告)日：2008-03-27
申请号：US11927030
申请日：2007-10-29
申请人： Franco Motika , Peitin Song
发明人： Franco Motika , Peitin Song
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/311
摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.
摘要翻译：测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环通过电路的预定操作周期。

112. 发明授权

US07308626B2 Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic 失效
标题翻译：基于皮秒成像 - 电路分析的内置自检诊断方法和结构
公开(公告)号：US07308626B2
公开(公告)日：2007-12-11
申请号：US10780878
申请日：2004-02-19
申请人： Franco Motika , Peilin Song
发明人： Franco Motika , Peilin Song
IPC分类号： G01R31/28
CPC分类号： G01R31/318547 , G01R31/311
摘要： A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of operations for the circuit.
摘要翻译：测试，诊断和监视电子电路的操作中的至少一个的方法（和结构）包括中断用于为电路的正常操作提供时钟的时钟信号，并且使用第二时钟信号重复循环通过电路的预定操作周期。

113. 发明授权

US07257745B2 Array self repair using built-in self test techniques 失效
标题翻译：使用内置自检技术进行阵列自修复
公开(公告)号：US07257745B2
公开(公告)日：2007-08-14
申请号：US11047419
申请日：2005-01-31
申请人： William V. Huott , Franco Motika , Pradip Patel , Daniel Rodko
发明人： William V. Huott , Franco Motika , Pradip Patel , Daniel Rodko
IPC分类号： G11C29/00 , G01R31/28 , G11C17/18
CPC分类号： G01R31/318572 , G01R31/318566
摘要： A soft-fust test algorithm is distributed on-chip from an ABSIT engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Using single-bit MISR error evaluation an ABSIT test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.
摘要翻译：软测试算法通过LSSD移位寄存器链从ABSIT引擎分布在片上，以动态评估多个阵列，对不良元素进行冗余补偿，并修复可修复的阵列。使用单位MISR错误评估，通过移位寄存器链在所有数组上同时执行一个ABSIT测试序列。如果任何阵列出现错误，则采用冗余补偿，并对所有可能的阵列冗余组合重复ABIST测试，直到每个阵列的功能配置被识别或已尝试所有可能的冗余组合。一旦功能阵列配置被验证，相关联的软保险丝状态可以用于熔断和/或提取用于进一步的系统设置，永久保险丝熔断和产量分析。可能需要由单独的ABIST引擎驱动的多个移位寄存器链来测试芯片上的所有阵列。

114. 发明申请

US20060236236A1 SYSTEM AND METHOD FOR MONITORING COMPUTER USER INPUT 失效
标题翻译：用于监视计算机用户输入的系统和方法
公开(公告)号：US20060236236A1
公开(公告)日：2006-10-19
申请号：US10907722
申请日：2005-04-13
申请人： Tijs Wilbrink , Edward Kelley , Franco Motika
发明人： Tijs Wilbrink , Edward Kelley , Franco Motika
IPC分类号： G06F17/00
CPC分类号： G06F11/3476 , G06F11/3485
摘要： A system and method for monitoring text input from a keyboard and from a pointing device, by monitoring input from a user keyboard for entry of text and cursor controls; monitoring input from a pointing device; logging keyboard entered text to a key log; and responsive to input selectively from the pointing device and keyboard selectively signaling a command action, determining text contents of the command action and logging the text contents to the key log in sequence with the keyboard entered text. A temporary storage is provided for storing copied content, and for storing pointing device input device definitions and key command definitions for each application. A log file stores a key log table for each application; and a key logger stores to the key log table entered text reconstructed with reference to the pointing device position, the copied content, the pointing device input device definitions, and the key command definitions.
摘要翻译：一种用于监视来自键盘和指点设备的文本输入的系统和方法，通过监视来自用户键盘的输入以输入文本和光标控制; 监视来自指点设备的输入; 记录键盘输入文本到键盘日志; 并且响应于来自所述指示设备和键盘的选择性地输入，选择性地发信号通知命令动作，确定所述命令动作的文本内容并且按照所述键盘输入的文本将所述文本内容记录到所述键记录。提供临时存储用于存储复制的内容，以及用于存储针对每个应用的指示设备输入设备定义和密钥命令定义。日志文件存储每个应用程序的密钥日志表; 并且键盘记录器存储到关键日志表中，输入的文本参考指示设备位置，复制内容，指点设备输入设备定义和键命令定义重建。

115. 发明申请

US20060212519A1 RFID WIRELESS CONTROL OF INSTANT MESSAGING 有权
标题翻译： RFID无线控制的即时消息传递
公开(公告)号：US20060212519A1
公开(公告)日：2006-09-21
申请号：US10906992
申请日：2005-03-15
申请人： Edward Kelley , Franco Motika , Tijs Wilbrink
发明人： Edward Kelley , Franco Motika , Tijs Wilbrink
IPC分类号： G06F15/16
CPC分类号： H04L63/0853 , H04L51/04 , H04L51/38 , H04L67/18 , H04L67/24
摘要： A remote control instant messaging method and system for automatically activating an instant messaging session based upon remote detection of a user approaching a processor capable of executing an instant message system. The method and system also automatically deactivate the instant messaging session based upon remote detection of the user's absence from such processor and automatically re-activate the instant messaging session based upon remote detection of the user's return to the processor. A second instant messaging session can also be remotely activated on a second processor operated by another user_id by detecting the first user's approach to such second processor. The first user is automatically disengaged from this second instant messaging session when the user leaves the location of the second processor.
摘要翻译：一种用于基于接近能够执行即时消息系统的处理器的用户的远程检测来自动激活即时消息收发会话的远程控制即时消息收发方法和系统。该方法和系统还基于远程检测用户离开这种处理器的缺点而自动停用即时消息接发会话，并且基于用户对处理器的返回的远程检测自动重新激活即时消息收发会话。通过检测第一用户对这种第二处理器的处理，也可以在由另一user_id操作的第二处理器上远程激活第二即时通讯会话。当用户离开第二处理器的位置时，第一用户将自动从第二即时消息接发中脱离。

116. 发明授权

US06968489B2 Pseudo random optimized built-in self-test 有权
标题翻译：伪随机优化内置自检
公开(公告)号：US06968489B2
公开(公告)日：2005-11-22
申请号：US10055275
申请日：2002-01-23
申请人： Franco Motika , Timothy J. Koprowski
发明人： Franco Motika , Timothy J. Koprowski
IPC分类号： G01R31/3181 , G01R31/3185 , G01R31/28 , G06F11/00
CPC分类号： G01R31/318385 , G01R31/31813 , G01R31/318547
摘要： Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern generation with either internal or external weight set selection. WRP patterns are generated by a tester either externally or internally to a device under test (DUT) and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.
摘要翻译：平坦伪随机测试模式与加权伪随机测试模式相结合提供，以便可以在每个周期改变应用于LSSD移位寄存器（SR）链中的每个锁存器的权重。这使得片内加权模式生成与内部或外部权重集合选择的集成。 WRP模式由测试仪在外部或内部生成到被测器件（DUT），并通过移位寄存器输入（SRI或WPI）加载到芯片的移位寄存器锁存器（SRL）中。测试（或LSSD测试器循环序列）包括使用WRP加载SR链中的SRL，脉冲相应的时钟，并将在SRL中捕获的响应卸载到多输入签名寄存器（MISR）中。然后可以对每个权重集合多次应用每个测试，权重集为每个SRL分配权重因子或概率。

117. 发明申请

US20050204237A1 Method and system for providing interactive testing of integrated circuits 失效
标题翻译：提供集成电路交互式测试的方法和系统
公开(公告)号：US20050204237A1
公开(公告)日：2005-09-15
申请号：US10789710
申请日：2004-02-27
申请人： Todd Burdine , Franco Motika , Peilin Song
发明人： Todd Burdine , Franco Motika , Peilin Song
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31703 , G01R31/318371 , G06F11/263
摘要： A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator. The method includes receiving a second failing region from the fault simulator, the second failing region created in response to the mismatches and the logic model, and the second failing region corresponding to a subset of the one or more circuits on the integrated circuit.
摘要翻译：一种用于提供集成电路的交互式和迭代测试的方法，包括接收第一故障区域。第一故障区域对应于集成电路上的一个或多个电路。该方法响应于第一故障区域和集成电路的逻辑模型生成针对一个或多个电路的一组自适应算法测试模式。确定测试模式的预期结果。该方法包括将测试图案应用于集成电路上的第一故障区域，从而得到测试图案的实际结果。对实际结果的预期结果进行比较。该方法还将预期结果与实际结果之间的错配传输到故障模拟器。该方法包括从故障模拟器接收第二故障区域，响应于不匹配和逻辑模型而创建的第二故障区域，以及对应于集成电路上的一个或多个电路的子集的第二故障区域。

118. 发明申请

US20050108599A1 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 有权
标题翻译：使用时钟门控或信号门控对设备进行分区以进行故障隔离和诊断数据采集
公开(公告)号：US20050108599A1
公开(公告)日：2005-05-19
申请号：US11006274
申请日：2004-12-07
申请人： Leendert Huisman , William Huott , Franco Motika , Leah Pfeifer Pastel
发明人： Leendert Huisman , William Huott , Franco Motika , Leah Pfeifer Pastel
IPC分类号： G01R31/319 , G01R31/3193 , G11B20/20 , G06F7/50 , G06K5/04 , G11B5/00
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.
摘要翻译：在一个方面，测试了通过使用时钟门控或信号门控被划分成段的电子设备。识别出作为故障来源的细分之一。将诊断程序应用于识别的段以确定故障的原因。

119. 发明授权

US06751765B1 Method and system for determining repeatable yield detractors of integrated circuits 失效
标题翻译：用于确定集成电路的可重复产量剔除器的方法和系统
公开(公告)号：US06751765B1
公开(公告)日：2004-06-15
申请号：US09722880
申请日：2000-11-27
申请人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
发明人： Richard F. Rizzolo , Rocco E. DeStefano , Joseph E. Eckelman , Thomas G. Foote , Steven Michnowski , Franco Motika , Phillip J. Nigh , Bryan J. Robbins
IPC分类号： G01R3128
CPC分类号： G01R31/3185
摘要： An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.
摘要翻译：本发明的示例性实施例是用于LBIST测试集成电路的方法。该方法包括生成多个多位测试模式，并且通过多个测试模式分区对多位测试模式进行分组，所述多个测试模式分区包括具有第一数量位的第一测试模式分区和具有第二数量位的第二测试模式分区大于第一个数字。将第一测试模式分区应用于集成电路以生成与第一参考签名进行比较以检测故障的第一签名。将第二测试模式分区应用于集成电路以产生与第二参考签名进行比较的第二签名，以检测集成电路中的故障。

120. 发明授权

US06671644B2 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 失效
公开(公告)号：US06671644B2
公开(公告)日：2003-12-30
申请号：US09930355
申请日：2001-08-15
申请人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
发明人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
IPC分类号： G06F1100
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

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