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111. 发明申请

US20060121715A1 Integrated circuit having gates and active regions forming a regular grating 失效
标题翻译：集成电路具有形成规则光栅的栅极和有源区
公开(公告)号：US20060121715A1
公开(公告)日：2006-06-08
申请号：US11065837
申请日：2005-02-25
申请人： Leland Chang , Hon-Sum Wong
发明人： Leland Chang , Hon-Sum Wong
IPC分类号： H01L21/44 , H01L21/8234 , H01L21/82
CPC分类号： H01L27/1104 , H01L27/11
摘要： A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.
摘要翻译：半导体器件包括可连接到一个或多个导体的多个可重复的电路单元，至少提供与电路单元的电连接和/或单元中的一个或多个电路元件之间的电连接。每个电路单元被配置成具有栅极和形成光栅的有源区，其中，对于器件中的给定有源层，每个有源区的宽度相对于彼此基本相同，任何两个相邻的有源区之间的间隔基本上相同，每个栅极的宽度相对于彼此基本相同，并且任何两个相邻栅极之间的间隔基本相同。

112. 发明授权

US08709888B2 Hybrid CMOS nanowire mesh device and PDSOI device 有权
标题翻译：混合CMOS纳米线网格装置和PDSOI装置
公开(公告)号：US08709888B2
公开(公告)日：2014-04-29
申请号：US13328069
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/72
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/088 , H01L27/1211 , H01L29/0673 , H01L29/66439 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和PDSOI器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和PDSOI器件的半导体结构。

113. 发明申请

US20130256763A1 LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION 有权
标题翻译： SRAM扩展中的低延伸剂量植入
公开(公告)号：US20130256763A1
公开(公告)日：2013-10-03
申请号：US13464267
申请日：2012-05-04
申请人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff.
摘要翻译：静态随机存取存储器制造阵列包括至少一个p型场效应晶体管，其包括栅极堆叠和形成具有栅极长度L gate和有效栅极长度的栅极的隔离间隔，Leff以及与栅极堆叠相邻的源极和漏极区域其中源极和漏极区域由低延伸剂量植入物形成，其降低了Lgate和Leff之间的差异。

114. 发明授权

US08531871B2 8-transistor SRAM cell design with Schottky diodes 有权
标题翻译：具有肖特基二极管的8晶体管SRAM单元设计
公开(公告)号：US08531871B2
公开(公告)日：2013-09-10
申请号：US13345619
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/00 , G11C11/417
CPC分类号： G11C11/417 , G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.
摘要翻译：一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。

115. 发明授权

US08502325B2 Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance 有权
标题翻译：具有用于降低寄生电容的硅侧壁的金属高K晶体管
公开(公告)号：US08502325B2
公开(公告)日：2013-08-06
申请号：US13432395
申请日：2012-03-28
申请人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
发明人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
IPC分类号： H01L21/70 , H01L27/12 , H01L21/02 , H01L29/78 , H01L21/338 , H01L21/8238 , H01L21/336 , H01L21/76 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823864 , H01L21/26586 , H01L21/28105 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656
摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.
摘要翻译：一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层，选择性地去除仅第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

116. 发明申请

US20130176770A1 8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES 有权
标题翻译：具有内部通孔结型二极管的8位晶体管SRAM单元设计
公开(公告)号：US20130176770A1
公开(公告)日：2013-07-11
申请号：US13345629
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译：一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到写入位线的每个通过栅极晶体管的源极或漏极; 导通栅极和下拉晶体管的共用源极/漏极端子处的内部结二极管，用于阻止从写位线到电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

117. 发明授权

US08460991B2 Differentially recessed contacts for multi-gate transistor of SRAM cell 失效
标题翻译： SRAM单元的多栅极晶体管的差分凹陷触点
公开(公告)号：US08460991B2
公开(公告)日：2013-06-11
申请号：US13547218
申请日：2012-07-12
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： C12N9/22
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A complementary metal-oxide-semiconductor static random access memory cell includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount.
摘要翻译：互补金属氧化物半导体静态随机存取存储单元包括多个P沟道多栅极晶体管和多个N沟道多栅极晶体管。每个晶体管包括栅电极和由至少一个栅极电极隔开的源极和漏极区域。 SRAM单元还包括形成在至少一个晶体管的源区和漏区内的多个触点。至少一个晶体管的多个触点凹入预定的凹陷量，其中至少一个晶体管的电阻基于预定的凹陷量而变化。

118. 发明授权

US08397183B2 Generation of asymmetric circuit devices 有权
标题翻译：生成不对称电路器件
公开(公告)号：US08397183B2
公开(公告)日：2013-03-12
申请号：US12699621
申请日：2010-02-03
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于创建适当的块级形状以制造不对称场效应晶体管（FET）。在一个实施例中，该方法包括获得具有有源区域电平（RX）和栅极区域电平（PC）的集成电路设计，RX和PC电平中的每一个具有表示半导体区域的多个形状; 并且从RX和PC级形状定义具有多个SD级形状的新级别SD。该方法还包括确定哪些新形状是源区，哪些是形成漏区; 确定哪个源区域正在向上，哪些指向下？并复制向上指向的源区域的形状和指向下一个额定的定义的级别的源区域的形状。

119. 发明申请

US20120313174A1 METHOD OF MAKING A MOSFET HAVING SELF-ALIGNED SILICIDED SCHOTTKY BODY TIE INCLUDING INTENTIONAL PULL-DOWN OF AN STI EXPOSING SIDEWALLS OF A DIFFUSION REGION 审中-公开
标题翻译：制造具有自对准硅酸钙肖特基体的MOSFET的方法，包括暴露在扩散区域的边缘的潜在的下拉
公开(公告)号：US20120313174A1
公开(公告)日：2012-12-13
申请号：US13590324
申请日：2012-08-21
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/78612 , H01L29/66772
摘要： A self-aligned transistor device includes: a source region and drain regions disposed on an oxide layer; a channel with a diffusion region formed between the drain and source regions; a silicide layer over a top surface of the source and drain regions, extending into the diffusion region; and a recess formed on each end of the device to expose sidewalls of the device to a free surface by performing shallow trench isolation on the oxide layer of the device that extends past the silicide layer.
摘要翻译：自对准晶体管器件包括：设置在氧化物层上的源极区域和漏极区域; 在漏极和源极区域之间形成有扩散区域的沟道; 在源极和漏极区域的顶表面上方的硅化物层，延伸到扩散区域中; 以及通过在延伸穿过硅化物层的器件的氧化物层上进行浅沟槽隔离，形成在器件的每个端部上的凹部以将器件的侧壁暴露于自由表面。

120. 发明申请

US20120276739A1 DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL 失效
标题翻译： SRAM单元的多栅极晶体管的不同接触的接触
公开(公告)号：US20120276739A1
公开(公告)日：2012-11-01
申请号：US13547218
申请日：2012-07-12
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/768
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： A complementary metal-oxide-semiconductor static random access memory cell includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount.
摘要翻译：互补金属氧化物半导体静态随机存取存储单元包括多个P沟道多栅极晶体管和多个N沟道多栅极晶体管。每个晶体管包括栅电极和由至少一个栅极电极隔开的源极和漏极区域。 SRAM单元还包括形成在至少一个晶体管的源区和漏区内的多个触点。至少一个晶体管的多个触点凹入预定的凹陷量，其中至少一个晶体管的电阻基于预定的凹陷量而变化。

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