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111. 发明授权

US07250651B2 Semiconductor memory device comprising memory cells with floating gate electrode and method of production 有权
标题翻译：半导体存储器件包括具有浮栅电极的存储单元和制造方法
公开(公告)号：US07250651B2
公开(公告)日：2007-07-31
申请号：US10921766
申请日：2004-08-19
申请人： Karl-Heinz Küsters , Josef Willer , Corvin Liaw
发明人： Karl-Heinz Küsters , Josef Willer , Corvin Liaw
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L31/062
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/51 , H01L29/66825 , H01L29/792
摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.
摘要翻译：位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。浮栅电极布置在所述上表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

112. 发明申请

US20070048993A1 Semiconductor product and method for forming a semiconductor product 有权
标题翻译：用于形成半导体产品的半导体产品和方法
公开(公告)号：US20070048993A1
公开(公告)日：2007-03-01
申请号：US11217122
申请日：2005-08-31
申请人： Josef Willer , Patrick Haibach , Christoph Kleint , Nicolas Nagel
发明人： Josef Willer , Patrick Haibach , Christoph Kleint , Nicolas Nagel
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.
摘要翻译：半导体产品包括具有基板表面的基板。多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。在字线之间提供多个导电接触结构。该产品还包括多个填充结构。每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。两个相应的接触结构在第一方向上彼此间隔一定距离。在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

113. 发明授权

US07119395B2 Memory cell with nanocrystals or nanodots 有权
标题翻译：具有纳米晶体或纳米点的记忆体
公开(公告)号：US07119395B2
公开(公告)日：2006-10-10
申请号：US10916013
申请日：2004-08-11
申请人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
发明人： Martin Gutsche , Josef Willer , Cay-Uwe Pinnow , Ralf Symanczyk
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).
摘要翻译：存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。栅电极（5）通过导电间隔物（7）在侧面加宽。

114. 发明授权

US07087950B2 Flash memory cell, flash memory device and manufacturing method thereof 有权
标题翻译：闪存单元，闪存设备及其制造方法
公开(公告)号：US07087950B2
公开(公告)日：2006-08-08
申请号：US10835390
申请日：2004-04-30
申请人： Josef Willer , Frank Lau
发明人： Josef Willer , Frank Lau
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/66818 , H01L29/7851 , H01L29/78645
摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.
摘要翻译：本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状包围所述有源区域的所述突出部分。本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

115. 发明申请

US20060145227A1 Method for producing semiconductor memory devices and integrated memory device 有权
标题翻译：用于制造半导体存储器件和集成存储器件的方法
公开(公告)号：US20060145227A1
公开(公告)日：2006-07-06
申请号：US11371743
申请日：2006-03-09
申请人： Josef Willer
发明人： Josef Willer
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/105 , H01L21/28282 , H01L27/11568 , H01L27/11573
摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.
摘要翻译：本发明提供了一种用于存储单元阵列，特别是电荷捕获存储单元阵列的集成方案，其包括局部互连的架构，其能够避免字线堆叠的氮化物绝缘并且在标准技术中产生不同结构和尺寸的CMOS器件以及更高级的存储单元晶体管。

116. 发明授权

US07061046B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07061046B2
公开(公告)日：2006-06-13
申请号：US10952233
申请日：2004-09-28
申请人： Josef Willer , Thomas Mikolajick
发明人： Josef Willer , Thomas Mikolajick
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/115 , H01L29/792
摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.
摘要翻译：位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

117. 发明申请

US20060120138A1 Semiconductor memory with volatile and non-volatile memory cells 审中-公开
标题翻译：具有易失性和非易失性存储单元的半导体存储器
公开(公告)号：US20060120138A1
公开(公告)日：2006-06-08
申请号：US11260691
申请日：2005-10-28
申请人： Corvin Liaw , Josef Willer , Michael Kund
发明人： Corvin Liaw , Josef Willer , Michael Kund
IPC分类号： G11C11/24
CPC分类号： G11C14/00 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C14/0045 , H01L27/105 , H01L27/10897 , H01L27/286 , H01L51/0595
摘要： The present invention relates to a semiconductor memory with a volatile memory device, in particular a DRAM memory device, and with a non-volatile memory device. The volatile memory device is electrically coupled with the non-volatile memory device, and the non-volatile memory device has a polymer memory device adapted to be switched between two states of information.
摘要翻译：本发明涉及具有易失性存储器件，特别是DRAM存储器件以及非易失性存储器件的半导体存储器。易失性存储器件与非易失性存储器件电耦合，并且非易失性存储器件具有适于在两种信息状态之间切换的聚合物存储器件。

118. 发明申请

US20060091448A1 Charge-trapping memory device and methods for operating and manufacturing the cell 有权
标题翻译：电荷捕获存储器件以及用于操作和制造电池的方法
公开(公告)号：US20060091448A1
公开(公告)日：2006-05-04
申请号：US11253939
申请日：2005-10-19
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.
摘要翻译：为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。栅电极层被构造成形成具有侧壁的栅电极。执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。然后可以沉积电荷捕获层材料以填充空间。然后在与栅电极相邻的半导体本体中形成源区和漏区。

119. 发明申请

US20060065921A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060065921A1
公开(公告)日：2006-03-30
申请号：US10952233
申请日：2004-09-28
申请人： Josef Willer , Thomas Mikolajick
发明人： Josef Willer , Thomas Mikolajick
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/115 , H01L29/792
摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.
摘要翻译：位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

120. 发明申请

US20050286296A1 Semiconductor memory having charge trapping memory cells and fabrication method 有权
标题翻译：具有电荷捕获存储单元的半导体存储器和制造方法
公开(公告)号：US20050286296A1
公开(公告)日：2005-12-29
申请号：US11145541
申请日：2005-06-03
申请人： Michael Bollu , Armin Kohlhase , Christoph Ludwig , Herbert Palm , Josef Willer
发明人： Michael Bollu , Armin Kohlhase , Christoph Ludwig , Herbert Palm , Josef Willer
IPC分类号： H01L21/8246 , H01L27/115 , G11C11/34
CPC分类号： H01L27/11568 , H01L27/115
摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.
摘要翻译：在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

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