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    • 114. 发明申请
    • MECHANISM FOR MEMORY REDUCTION IN PICTURE-IN-PICTURE VIDEO GENERATION
    • 用于图像图像视频生成中的存储器减少的机制
    • US20140111691A1
    • 2014-04-24
    • US14145736
    • 2013-12-31
    • Daekyeung KimWooseung YangYoung II KimJeoong Sung ParkHoon Choi
    • Daekyeung KimWooseung YangYoung II KimJeoong Sung ParkHoon Choi
    • G06T1/60G06T3/40H04N9/64H04N5/45
    • G06T1/60G06T3/4084H04N5/45H04N9/641H04N21/2365H04N21/4316H04N21/4347H04N21/44004H04N21/440263
    • A mechanism for memory reduction in picture-in-picture video generation is disclosed. A method of embodiments of the invention includes receiving, from a transmitting device, a plurality of video streams at a receiving device coupled to the transmitting device, wherein a first video stream of the plurality of video streams is designated to be displayed as a main video and one or more other video streams of the plurality of video streams are designated to be displayed as one or more sub videos to the main video. The method further includes transforming the one or more other video streams into the one or more sub videos, temporarily holding the one or more sub videos in a compressed frame buffer, and merging, via pixel replacement, the main video and the one or more sub videos into a final video image capable of being displayed on a single screen utilizing a display device, wherein pixel replacement is performed such that the one or more sub videos occupy one or more sections of pixels of screen space pixels occupied by the main video.
    • 公开了一种用于画中画视频生成中的存储器减少的机构。 本发明的实施例的方法包括:在发送设备处,在耦合到所述发送设备的接收设备处从所述发送设备接收多个视频流,其中,所述多个视频流中的第一视频流被指定为被显示为主视频 并且指定多个视频流中的一个或多个其它视频流被显示为主视频的一个或多个子视频。 该方法还包括将一个或多个其他视频流变换成一个或多个子视频,将一个或多个子视频暂时保存在压缩帧缓冲器中,并通过像素替换合并主视频和一个或多个子视频 将视频转换为能够使用显示设备在单个屏幕上显示的最终视频图像,其中执行像素替换,使得所述一个或多个子视频占据主视频所占据的屏幕空间像素的一个或多个像素部分。
    • 116. 发明授权
    • Display apparatus
    • 显示装置
    • US08595403B2
    • 2013-11-26
    • US13241465
    • 2011-09-23
    • Hoon ChoiJae-hyun JeongKwang-youn Kim
    • Hoon ChoiJae-hyun JeongKwang-youn Kim
    • G06F13/00
    • G09G3/2092G09G2370/16
    • Provided is a display apparatus including an image processing module and a display main body, wherein the image processing module includes: an image signal processor processing an image signal; a module terminal transmitting the processed image signal in a wired manner; and a module wireless communication unit transmitting wirelessly the processed image signal, and wherein the display main body includes: a main body terminal receiving the image signal from the module terminal which is detachably connected to the main body terminal; a main body wireless communication unit receiving the image signal from the module wireless communication unit; and a display unit displaying an image corresponding to the image signal; and a controller controlling the image signal to be transmitted selectively from the module terminal to the main body terminal or from the module wireless communication unit to the main body wireless communication unit.
    • 提供一种包括图像处理模块和显示器主体的显示装置,其中图像处理模块包括:图像信号处理器处理图像信号; 模块终端以有线的方式发送处理后的图像信号; 以及模块无线通信单元,对所处理的图像信号进行无线传输,并且其中所述显示器主体包括:主体终端,其从所述模块终端接收可拆卸地连接到所述主体终端的图像信号; 主体无线通信单元,从模块无线通信单元接收图像信号; 以及显示单元,显示与图像信号相对应的图像; 以及控制图像信号的控制器,其选择性地从模块终端发送到主体终端,或者从模块无线通信单元发送到主体无线通信单元。
    • 120. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08179179B2
    • 2012-05-15
    • US12881541
    • 2010-09-14
    • Min-Su ParkHoon Choi
    • Min-Su ParkHoon Choi
    • H03H11/16
    • H03L7/0812G11C7/222
    • A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.
    • 半导体器件包括:复位信号发生器,被配置为根据外部时钟的频率改变多个复位信号中的激活信号数;多个混合控制信号发生器,被配置为产生多个第一和第二混合控制信号 以及时钟混频器,被配置为通过混合第一驱动时钟和第二驱动时钟来产生混频时钟,其中通过根据多个第一混频控制信号驱动外部时钟的正时钟来产生第一驱动时钟,以及 通过根据多个第二混合控制信号驱动外部时钟的负时钟来产生第二驱动时钟。