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111. 发明授权

US08558240B2 Thin film transistor display panel having a gate wire with different thicknesses and manufacturing method thereof 有权
标题翻译：具有不同厚度的栅极线的薄膜晶体管显示面板及其制造方法
公开(公告)号：US08558240B2
公开(公告)日：2013-10-15
申请号：US13010656
申请日：2011-01-20
申请人： Hyung-Jun Kim , Chang-Oh Jeong , Jae-Hong Kim
发明人： Hyung-Jun Kim , Chang-Oh Jeong , Jae-Hong Kim
IPC分类号： H01L27/14
CPC分类号： H01L29/6675 , G02F1/136213 , G02F1/136286 , G02F2001/13629 , H01L27/124 , H01L29/42384
摘要： A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.
摘要翻译：薄膜晶体管显示面板包括衬底，衬底上的栅极线，并且包括栅极线和栅电极; 栅极线上的栅极绝缘层; 栅极绝缘层上的半导体层; 数据线，包括半导体层上的源电极，与源电极相对于栅电极相对的漏电极和数据线; 数据线上的钝化层具有暴露漏电极的接触孔; 以及钝化层上的像素电极，并通过接触孔与漏电极连接。栅极线分别具有栅极线和栅电极所在的第一区域和第二区域。第一区域中的栅极线的厚度大于第二区域中的栅极线的厚度。

112. 发明授权

US08486775B2 Thin film transistor array panel and method for manufacturing the same 有权
公开(公告)号：US08486775B2
公开(公告)日：2013-07-16
申请号：US13020467
申请日：2011-02-03
申请人： Byoung-June Kim , Jae-Ho Choi , Chang-Oh Jeong , Sung-Hoon Yang , Je-Hun Lee , Do-Hyun Kim , Hwa-Yeul Oh , Yong-Mo Choi
发明人： Byoung-June Kim , Jae-Ho Choi , Chang-Oh Jeong , Sung-Hoon Yang , Je-Hun Lee , Do-Hyun Kim , Hwa-Yeul Oh , Yong-Mo Choi
IPC分类号： H01L21/84
CPC分类号： H01L27/1255 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L29/41733 , H01L29/4908 , H01L29/66742 , H01L29/66765
摘要： A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

113. 发明授权

US08199297B2 Display panel and method for manufacturing the same 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US08199297B2
公开(公告)日：2012-06-12
申请号：US12354115
申请日：2009-01-15
申请人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
发明人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
IPC分类号： G02F1/136 , G02F1/1343
CPC分类号： H01L33/0041 , H01L27/124 , H01L29/458
摘要： A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.
摘要翻译：显示面板包括：下栅极线，基本上垂直于下栅极线设置的下数据线，连接到下栅极线和下数据线的薄膜晶体管（“TFT”），设置在下栅极线上的绝缘层，下数据线和TFT，并且具有暴露下栅极线和下数据线的多个沟槽，设置在下栅极线上的沟槽中的上栅极线，设置在下数据上的沟槽中的上数据线线和与TFT连接的像素电极。

114. 发明授权

US08198657B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08198657B2
公开(公告)日：2012-06-12
申请号：US12652379
申请日：2010-01-05
申请人： Dong-Hoon Lee , Do-Hyun Kim , Chang-Oh Jeong , O-Sung Seo , Xin-Xing Li
发明人： Dong-Hoon Lee , Do-Hyun Kim , Chang-Oh Jeong , O-Sung Seo , Xin-Xing Li
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L27/124 , H01L29/78618
摘要： A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板。在绝缘基板上形成栅极线，并具有栅电极。在栅极线上形成栅绝缘层。半导体层形成在栅极绝缘层上并与栅电极重叠。在半导体层上形成扩散阻挡层并含有氮。数据线与栅极线交叉，并且具有部分地接触扩散阻挡层的源电极和部分地接触扩散阻挡层并面向源电极的漏电极。漏电极在栅电极上。像素电极电连接到漏电极。

115. 发明授权

US07968385B2 Thin film transistor panel and fabricating method thereof 有权
标题翻译：薄膜晶体管面板及其制造方法
公开(公告)号：US07968385B2
公开(公告)日：2011-06-28
申请号：US12605566
申请日：2009-10-26
申请人： Chang-Oh Jeong , Dong-Hoon Lee
发明人： Chang-Oh Jeong , Dong-Hoon Lee
IPC分类号： H01L21/00
CPC分类号： H01L27/12 , H01L27/124 , H01L29/41733 , H01L29/66765
摘要： A thin film transistor panel includes; an insulating substrate, a gate line including a gate electrode disposed on the insulating substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including a sidewall, a data line including a source electrode disposed on the semiconductor layer, a drain electrode disposed substantially opposite to and spaced apart from the source electrode, a first protective film disposed on the data line, the first protective film including a sidewall, a second protective film disposed on the first protective film and including a sidewall, and a pixel electrode electrically connected to the drain electrode, wherein the sidewall of the second protective film is disposed inside an area where the sidewall of the first protective film is disposed, and the source electrode and the drain electrode cover the sidewall of the semiconductor layer.
摘要翻译：薄膜晶体管面板包括：绝缘基板，包括设置在绝缘基板上的栅电极的栅极线，设置在栅极上的栅极绝缘层，设置在栅极绝缘层上的半导体层，包括侧壁的半导体层，包括源极的数据线设置在所述半导体层上的电极，与所述源极电极基本相对并间隔设置的漏电极，设置在所述数据线上的第一保护膜，所述第一保护膜包括侧壁，设置在所述第一保护膜上的第二保护膜并且包括侧壁和与漏电极电连接的像素电极，其中第二保护膜的侧壁设置在设置有第一保护膜的侧壁的区域的内侧，源电极和漏电极覆盖半导体层的侧壁。

116. 发明申请

US20110124163A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110124163A1
公开(公告)日：2011-05-26
申请号：US13020467
申请日：2011-02-03
申请人： Byoung-June KIM , Jae-Ho Choi , Chang-Oh Jeong , Sung-Hoon Yang , Je-Hun Lee , Do-Hyun Kim , Hwa-Yeul Oh , Yong-Mo Choi
发明人： Byoung-June KIM , Jae-Ho Choi , Chang-Oh Jeong , Sung-Hoon Yang , Je-Hun Lee , Do-Hyun Kim , Hwa-Yeul Oh , Yong-Mo Choi
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L27/1255 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L29/41733 , H01L29/4908 , H01L29/66742 , H01L29/66765
摘要： A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.
摘要翻译：薄膜晶体管（TFT）的制造方法包括形成包括可以与硅组合的金属的栅电极，以在衬底上形成硅化物，并通过在栅极电极中向栅电极提供包括硅的气体形成栅极绝缘层该方法还包括在栅极绝缘层上形成半导体，在半导体上形成数据线和漏极并形成连接到漏电极的像素电极。

117. 发明授权

US07923287B2 Thin film transistor substrate having transparent conductive metal and method of manufacturing the same 有权
标题翻译：具有透明导电金属的薄膜晶体管基板及其制造方法
公开(公告)号：US07923287B2
公开(公告)日：2011-04-12
申请号：US12001031
申请日：2007-12-06
申请人： Eun-Guk Lee , Do-Hyun Kim , Chang-Oh Jeong , Je-Hun Lee , Soon-Kwon Lim
发明人： Eun-Guk Lee , Do-Hyun Kim , Chang-Oh Jeong , Je-Hun Lee , Soon-Kwon Lim
IPC分类号： H01L21/84 , H01L29/786
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/45 , H01L29/7869
摘要： A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.
摘要翻译：公开了一种薄膜晶体管基板及其制造方法。制造薄膜晶体管基板的方法包括在基板上形成包括栅极线，栅电极和下栅极焊盘电极的第一导电图案组，在基板上形成栅极绝缘层，第一导电图案组形成，在所述栅极绝缘层上形成与所述栅电极重叠的氧化物半导体图案，以及在其上形成有所述氧化物半导体图案的所述基板上形成第一和第二导电层，并且对所述第一导电层和所述第二导电层进行构图以形成第二导电图案包括数据线，源电极，漏电极和数据焊盘。

118. 发明申请

US20110031117A1 SPUTTERING TARGET APPARATUS 有权
标题翻译：喷射目标装置
公开(公告)号：US20110031117A1
公开(公告)日：2011-02-10
申请号：US12779459
申请日：2010-05-13
申请人： Do-Hyun KIM , Dong-Hoon Lee , Chang-Oh Jeong
发明人： Do-Hyun KIM , Dong-Hoon Lee , Chang-Oh Jeong
IPC分类号： C23C14/34
CPC分类号： C23C14/3407 , C23C14/3464 , H01J37/342 , H01J37/3435
摘要： A sputtering target apparatus is provided. The sputtering target apparatus includes a first target assembly including a first target array having a first target, a second target disposed adjacent to the first target, and a first target dividing region disposed between the first and second targets, the first target assembly extending along a first direction, wherein the first target dividing region has a longitudinal cross-section that is oblique with respect to the first direction.
摘要翻译：提供溅射靶设备。溅射靶设备包括：第一目标组件，其包括具有第一靶的第一靶阵列，与第一靶相邻设置的第二靶;以及设置在第一靶和第二靶之间的第一靶分离区，第一方向，其中第一目标分割区域具有相对于第一方向倾斜的纵向横截面。

119. 发明授权

US07767478B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07767478B2
公开(公告)日：2010-08-03
申请号：US12031121
申请日：2008-02-14
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L21/00
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

120. 发明申请

US20100022041A1 THIN FILM TRANSISTOR ARRAY PANEL INCLUDING LAYERED LINE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列包括层状线结构及其制造方法
公开(公告)号：US20100022041A1
公开(公告)日：2010-01-28
申请号：US12576217
申请日：2009-10-08
申请人： Je-Hun LEE , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun LEE , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L21/16
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/124
摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
摘要翻译：本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

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