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111. 发明申请

US20100214825A1 Programming MRAM Cells Using Probability Write 有权
标题翻译：使用概率写入编程MRAM单元
公开(公告)号：US20100214825A1
公开(公告)日：2010-08-26
申请号：US12617982
申请日：2009-11-13
申请人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
发明人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/1677 , G11C11/1675
摘要： A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell.
摘要翻译：写入磁阻随机存取存储器（MRAM）单元的方法包括提供写入脉冲以将值写入MRAM单元; 以及在提供第一写入脉冲的步骤之后立即验证MRAM单元的状态。在写入失败的情况下，该值被重写到MRAM单元中。

112. 发明授权

US07723803B2 Bipolar device compatible with CMOS process technology 有权
标题翻译：双极器件兼容CMOS工艺技术
公开(公告)号：US07723803B2
公开(公告)日：2010-05-25
申请号：US11075141
申请日：2005-03-07
申请人： Shine Chung
发明人： Shine Chung
IPC分类号： H01L29/739
CPC分类号： H01L29/735 , H01L21/8249 , H01L29/0692 , H01L29/0821
摘要： The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.
摘要翻译：本发明公开了一种双极器件。在半导体衬底中形成发射极。收集器与衬底中的发射极横向间隔开。栅极端子形成在衬底上，限定发射极和集电极之间的空间。在基板上形成了与发射极或集电极相距预定距离的非本征基极，其中基极，发射极，集电极和栅极端子位于由围绕隔离结构的孔中限定的有源区域中基质。

113. 发明授权

US07719909B2 DRAM writing ahead of sensing scheme 有权
标题翻译： DRAM写入领先感应方案
公开(公告)号：US07719909B2
公开(公告)日：2010-05-18
申请号：US12100329
申请日：2008-04-09
申请人： Shine Chung , Cheng-Hsien Hung
发明人： Shine Chung , Cheng-Hsien Hung
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C11/4096 , G11C11/4097
摘要： This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.
摘要翻译：本发明公开了一种用于半导体存储器的写入感测电路，其具有至少一个具有连续字线的存储器块，该存储器块连接到存储器块的列中的所有存储器单元，并且连续位线耦合到所有存储器所述写入感测电路包括属于相同存储块的第一和第二读出放大器，耦合在所述第一读出放大器与第一电源之间的第一开关器件，所述第一开关器件为由第一信号控制的第二开关装置和耦合在第二读出放大器与第一电源之间的第二开关装置，第二开关装置由不同于第一信号的第二信号控制，其中当第一读出放大器被激活时，读出放大器可以保持不激活。

114. 发明授权

US07605577B2 Start-up circuit for a bandgap circuit 有权
标题翻译：带隙电路的启动电路
公开(公告)号：US07605577B2
公开(公告)日：2009-10-20
申请号：US11605501
申请日：2006-11-29
申请人： Shine Chung
发明人： Shine Chung
IPC分类号： G05F3/16 , G05F1/10
CPC分类号： G05F3/30 , G05F1/468
摘要： A startup circuit operating with a bandgap circuit having a predetermined node with a current change proportional to temperature change and a current source connected to the predetermined node comprising: a controllable current switch connected between the predetermined node and a control node of the current source; wherein when the voltage at the predetermined node is floating when starting the bandgap circuit, the controllable current switch biases the current source at the control node whereby the voltage at the predetermined node changes based on the current provided by the current source causing the bandgap circuit to start its normal operation.
摘要翻译：一种具有带隙电路的启动电路，该带隙电路具有与温度变化成比例的电流变化的预定节点和连接到预定节点的电流源，包括：连接在预定节点和电流源的控制节点之间的可控电流开关; 其中，当启动带隙电路时，当预定节点处的电压为浮置时，可控电流开关偏置控制节点处的电流源，由此基于由电流源提供的电流使预定节点处的电压改变，导致带隙电路开始正常运行。

115. 发明申请

US20090166872A1 Memory Word lines with Interlaced Metal Layers 有权
标题翻译：内存字线与隔行金属层
公开(公告)号：US20090166872A1
公开(公告)日：2009-07-02
申请号：US12100866
申请日：2008-04-10
申请人： Shine Chung , Cheng-Hsien Hung
发明人： Shine Chung , Cheng-Hsien Hung
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L27/105 , H01L27/10894
摘要： A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance.
摘要翻译：公开了一种具有改进的字线结构的存储器件。存储器件包括在衬底上基本上彼此平行的多个多晶硅条，多个多晶硅条布置在第一组和第二组的两个交替组中。存储器件还包括形成多个位线的第一层导电条和第二层餐条，第二层导电条覆盖在多晶硅条上并耦合到第一组多晶硅条。此外，存储器件包括形成一个或多个电源线的第三层导电条和第四层金属条，第四层导电条覆盖在第二层导电条上，并连接到第二组多晶硅条以形成具有低电阻的新字线结构。

116. 发明申请

US20080224785A1 Temperature tracking oscillator circuit 有权
标题翻译：温度跟踪振荡电路
公开(公告)号：US20080224785A1
公开(公告)日：2008-09-18
申请号：US11717403
申请日：2007-03-13
申请人： Shine Chung , Jonathan Hung
发明人： Shine Chung , Jonathan Hung
IPC分类号： H03K3/02
CPC分类号： H03K3/0231 , G11C7/04 , G11C11/406 , G11C11/40626 , G11C2211/4061 , H03K3/03
摘要： A temperature-dependent oscillator includes a first current source, wherein a first current provided by the first current source has a positive temperature coefficient, a second current source serially connected to the first current source, wherein a second current provided by the second current source has a negative temperature coefficient, and a capacitor serially connected to the first current source and parallel connected to the second current source.
摘要翻译：温度依赖振荡器包括第一电流源，其中由第一电流源提供的第一电流具有正温度系数，串联连接到第一电流源的第二电流源，其中由第二电流源提供的第二电流具有串联连接到第一电流源并并联连接到第二电流源的电容器。

117. 发明授权

US07376027B1 DRAM concurrent writing and sensing scheme 有权
标题翻译： DRAM并发写入和感测方案
公开(公告)号：US07376027B1
公开(公告)日：2008-05-20
申请号：US11593776
申请日：2006-11-07
申请人： Shine Chung , Cheng-Hsien Hung
发明人： Shine Chung , Cheng-Hsien Hung
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C11/4096 , G11C11/4097
摘要： This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source.
摘要翻译：本发明公开了一种用于半导体存储器的写入感测电路，包括形成互补BL对的第一和第二局部位线（BL），形成互补GBL对的第一和第二全局位线（GBL）至少一个由第一和第二GBL控制的开关电路，并且可控制地将预定电源连接到第一和第二BL，其中当在写入操作期间第一和第二GBL被断言时，开关电路只耦合第一和第二BL到预定电压源。

118. 发明申请

US20070026628A1 Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses 有权
标题翻译：用于减少由于浅沟槽隔离导致的氧化物应力引起的器件失配的器件结构
公开(公告)号：US20070026628A1
公开(公告)日：2007-02-01
申请号：US11189940
申请日：2005-07-26
申请人： Shine Chung , David Lu
发明人： Shine Chung , David Lu
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , H01L21/823481 , H01L27/0203
摘要： A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.
摘要翻译：公开了用于减少由于沟槽隔离相关应力引起的器件失配的电路和方法。一个或多个延伸的有源区形成在衬底上，其中有源区从其一个或多个端部延伸，并且一个或多个操作装置放置在一个或多个有源区上，其中延伸的有源区具有至少一个长度两个相邻操作装置的门之间的距离的两倍。

119. 发明申请

US20060028777A1 Method and system to protect electrical fuses 有权
标题翻译：保护电气保险丝的方法和系统
公开(公告)号：US20060028777A1
公开(公告)日：2006-02-09
申请号：US11010036
申请日：2004-12-10
申请人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
发明人： Shine Chung , Jiann-Tseng Huang , Shao-Chang Huang
IPC分类号： H02H9/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A method and system is disclosed for protecting electrical fuse circuitries. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.
摘要翻译：公开了一种用于保护电熔丝电路的方法和系统。具有静电放电（ESD）保护的电熔丝电路具有至少一个电熔丝，与至少一晶体管串联耦合的编程装置，用于接收用于控制流经电熔丝的编程电流的控制信号，电压源耦合到熔丝和用于提供编程电流的编程装置，以及保护模块，其在其第一端耦合到晶体管的栅极，以减少由于到达电压的电静电而在晶体管的栅极处累积的电荷源，从而防止编程设备意外编程保险丝。

120. 发明申请

US20050259495A1 Multiple-time programmable resistance circuit 有权
标题翻译：多次可编程电阻电路
公开(公告)号：US20050259495A1
公开(公告)日：2005-11-24
申请号：US10993734
申请日：2004-11-19
申请人： Shine Chung
发明人： Shine Chung
IPC分类号： G11C5/00 , G11C16/02 , G11C17/06 , G11C17/16
CPC分类号： G11C11/5692 , G11C16/02 , G11C17/16 , G11C2211/5646
摘要： Fuse circuit designs and the use thereof are disclosed. In one example, a fuse circuit providing predictable total resistances for multiple rounds of programming comprises a predetermined number of fuse stages coupled in series. Each stage comprises a first and a second connecting nodes, a fuse connected between the first and second connecting nodes, a first resistor with its first end connected to the first connecting node, and a second resistor with its first end connected to the second connecting node, wherein the first and second resistors connect to a third and a fourth connecting nodes, which are the first and second connecting nodes of a next fuse stage respectively, through their second ends.
摘要翻译：公开了熔断器电路设计及其应用。在一个示例中，为多次编程提供可预测的总电阻的熔丝电路包括串联耦合的预定数量的熔丝级。每个级包括第一和第二连接节点，连接在第一和第二连接节点之间的熔丝，第一电阻器，其第一端连接到第一连接节点，第二电阻器的第一端连接到第二连接节点其中所述第一和第二电阻器分别通过其第二端连接到第三和第四连接节点，所述第三和第四连接节点是下一个熔断器级的第一和第二连接节点。

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