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111. 发明授权

US08859375B2 High voltage device and manufacturing method thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US08859375B2
公开(公告)日：2014-10-14
申请号：US13317401
申请日：2011-10-17
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L21/336 , H01L21/266 , H01L29/08 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号： H01L29/0878 , H01L21/266 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/086 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中，其中衬底包括限定器件区域的隔离区域。高电压装置包括：位于器件区域中的掺杂有第二导电类型杂质的漂移区; 在器件区域和衬底的表面上的栅极; 以及在栅极的不同侧的器件区域中的第二导电类型源极和漏极。从俯视图，漂移区域的第二导电型杂质的浓度沿水平方向和垂直方向大致周期性地分布。

112. 发明授权

US08710551B2 High electron mobility transistor and manufacturing method thereof 有权
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US08710551B2
公开(公告)日：2014-04-29
申请号：US13597599
申请日：2012-08-29
申请人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
发明人： Chih-Fang Huang , Chien-Wei Chiu , Ting-Fu Chang , Tsung-Yu Yang , Tsung-Yi Huang
IPC分类号： H01L31/109 , H01L31/072
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/41766 , H01L29/7787
摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.
摘要翻译：本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT包括半导体层，半导体层上的势垒层，阻挡层上的压电层，压电层上的栅极，栅极两侧的源极和漏极，其中半导体的每个带隙层，阻挡层和压电层部分但不完全与其它两个带隙重叠。栅极形成为用于接收栅极电压。二维电子气体（2DEG）形成在半导体层和阻挡层之间的结的一部分中，但不在压电层的至少一部分下方，其中2DEG电连接到源极和漏极。

113. 发明授权

US08686500B2 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US08686500B2
公开(公告)日：2014-04-01
申请号：US13476043
申请日：2012-05-21
申请人： Tsung-Yi Huang , Ching-Yao Yang
发明人： Tsung-Yi Huang , Ching-Yao Yang
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/1083 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件形成在第一导电型衬底中，并且包括第二导电型高电压阱，场氧化物区域，栅极，第二导电型源极，第二导电型漏极，第一导电型体区域和第一导电型深井。深井在垂直方向上形成在高压井的下方并与其相邻。深井和高压阱由相同的光刻工艺步骤定义。

114. 发明申请

US20140048815A1 SCHOTTKY BARRIER DIODE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：肖特彼勒二极管及其制造方法
公开(公告)号：US20140048815A1
公开(公告)日：2014-02-20
申请号：US13589784
申请日：2012-08-20
申请人： Tsung-Yi Huang , Chien-Wei Chiu , Chih-Fang Huang , Tsung-Yu Yang
发明人： Tsung-Yi Huang , Chien-Wei Chiu , Chih-Fang Huang , Tsung-Yu Yang
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/66143
摘要： A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer.
摘要翻译：公开了一种肖特基势垒二极管（SBD），其包括：形成在衬底上的氮化镓（GaN）层; 在GaN层上形成的氮化镓铝（AlGaN）; 形成在AlGaN层上的绝缘层; 形成在所述绝缘层上的阳极导电层，其中在所述阳极导电层的一部分和所述AlGaN层之间或所述阳极导电层和所述GaN层的一部分之间形成肖特基接触，并且所述阳极导电层的另一部分通过绝缘层与AlGaN层分离; 以及形成在所述AlGaN层上的阴极导电层，其中在所述阴极导电层和所述GaN层之间或所述阴极导电层与所述AlGaN层之间形成欧姆接触，并且其中所述阳极导电层不直接连接到所述阴极导电层阴极导电层。

115. 发明申请

US20140045314A1 HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US20140045314A1
公开(公告)日：2014-02-13
申请号：US14056613
申请日：2013-10-17
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/66
CPC分类号： H01L29/66681 , H01L29/0623 , H01L29/1083 , H01L29/66659 , H01L29/7813 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在衬底中。高电压装置包括：栅极，源极和漏极，漂移区和缓解区。栅极形成在衬底的上表面上。源极和漏极分别位于栅极下方的两侧，源极和漏极由栅极分开。漂移区域至少位于栅极和漏极之间。缓冲区形成在漂移区下方，漂移区具有靠近源的边。漂移区域的这个边缘与缓解区域之间的垂直距离小于或等于漂移区域的深度的五倍。

116. 发明申请

US20140021544A1 Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof 有权
公开(公告)号：US20140021544A1
公开(公告)日：2014-01-23
申请号：US13555163
申请日：2012-07-22
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66689 , H01L29/7816
摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

117. 发明申请

US20130307072A1 Double Diffused Metal Oxide Semiconductor Device and Manufacturing Method Thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20130307072A1
公开(公告)日：2013-11-21
申请号：US13476043
申请日：2012-05-21
申请人： Tsung-Yi Huang , Ching-Yao Yang
发明人： Tsung-Yi Huang , Ching-Yao Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/1083 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device is formed in a first conductive type substrate, and includes a second conductive type high voltage well, a field oxide region, a gate, a second conductive type source, a second conductive type drain, a first conductive type body region, and a first conductive type deep well. The deep well is formed beneath and adjacent to the high voltage well in a vertical direction. The deep well and the high voltage well are defined by a same lithography process step.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件形成在第一导电型衬底中，并且包括第二导电型高电压阱，场氧化物区域，栅极，第二导电型源极，第二导电型漏极，第一导电型体区域和第一导电型深井。深井在垂直方向上形成在高压井的下方并与其相邻。深井和高压阱由相同的光刻工艺步骤定义。

118. 发明申请

US20130256680A1 Vertical Semiconductor Device and Manufacturing Method Thereof 有权
标题翻译：立式半导体器件及其制造方法
公开(公告)号：US20130256680A1
公开(公告)日：2013-10-03
申请号：US13436665
申请日：2012-03-30
申请人： Chien-Wei Chiu , Tsung-Yi Huang
发明人： Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/24 , H01L21/331 , H01L21/329 , H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L29/2003 , H01L29/66212 , H01L29/6631 , H01L29/66333 , H01L29/732 , H01L29/7395 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.
摘要翻译：本发明公开了一种立式半导体器件及其制造方法。所述垂直半导体器件包括：具有第一表面和第二表面的衬底，所述衬底包括由穿过所述衬底的多个导电插塞形成的导电阵列; 形成在所述第一表面上的半导体层，所述半导体层具有第三表面和第四表面，其中所述第四表面面向所述第一表面; 形成在第三表面上的第一电极; 以及形成在所述第二表面上用于电连接到所述导电阵列的第二电极。

119. 发明授权

US08525258B2 Method for controlling impurity density distribution in semiconductor device and semiconductor device made thereby 有权
标题翻译：用于控制由此制造的半导体器件和半导体器件中的杂质浓度分布的方法
公开(公告)号：US08525258B2
公开(公告)日：2013-09-03
申请号：US12817413
申请日：2010-06-17
申请人： Tsung-Yi Huang , Ying-Shiou Lin
发明人： Tsung-Yi Huang , Ying-Shiou Lin
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L21/26513 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.
摘要翻译：本发明公开了一种用于控制半导体器件中的杂质浓度分布的方法和由此制成的半导体器件。控制方法包括以下步骤：提供基板; 限定包括至少一个第一区域的掺杂区域; 通过掩模图案部分地掩蔽所述第一区域; 以及在所述掺杂区域中掺杂杂质以在所述第一区域中形成一个积分掺杂区域，由此所述第一区域的杂质浓度低于所述第一区域未被所述掩模图案掩蔽的情况。

120. 发明授权

US08421150B2 High voltage device and manufacturing method thereof 有权
标题翻译：高压器件及其制造方法
公开(公告)号：US08421150B2
公开(公告)日：2013-04-16
申请号：US13197370
申请日：2011-08-03
申请人： Tsung-Yi Huang , Huan-Ping Chu
发明人： Tsung-Yi Huang , Huan-Ping Chu
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中，其中衬底具有上表面。高压器件包括：形成在衬底中的第二导电型掩埋层; 第一导电型阱，其形成在上表面和埋层之间; 以及第二导电型阱，其连接到第一导电类型阱并且位于不同的水平位置。第二导电类型阱包括井下表面，其具有第一部分和第二部分，其中第一部分直接在掩埋层的上方并电耦合到掩埋层; 并且第二部分不位于掩埋层的上方并与衬底形成PN结。

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