专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

111. 发明授权

US07246215B2 Systolic memory arrays 有权
标题翻译：收缩记忆阵列
公开(公告)号：US07246215B2
公开(公告)日：2007-07-17
申请号：US10721178
申请日：2003-11-26
申请人： Shih-Lien L. Lu , Dinesh Somasekhar , Yibin Ye
发明人： Shih-Lien L. Lu , Dinesh Somasekhar , Yibin Ye
IPC分类号： G06F12/00
CPC分类号： G11C7/1039 , G06F13/1615 , G06F2212/271 , G11C7/10
摘要： A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.
摘要翻译：短暂的延迟和高带宽存储器包括细分为多个存储器阵列的收缩记忆体，包括存储这些存储体的存储体和管线。由于每个存储体的尺寸较小，访问速度更快，因此可以实现更短的延迟和更快的性能。由于流水线而实现了高吞吐量。使用提出的读写机制，在流水线频率处访问存储器。存储器中的每个存储单元都相同并重复，因此减少了设计复杂度。重新配置和组织存储器阵列大小以适应所需的大小和面积参数。

112. 发明申请

US20070004162A1 Capacitor structure for a logic process 有权
标题翻译：逻辑过程的电容结构
公开(公告)号：US20070004162A1
公开(公告)日：2007-01-04
申请号：US11170504
申请日：2005-06-29
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： H01L21/331
CPC分类号： H01L27/108 , H01L27/1085 , H01L28/40
摘要： A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.
摘要翻译：公开了制造金属绝缘体金属（MIM）电容器的制造工艺改进。 MIM电容器可以用在诸如DRAM的存储器单元中，并且还可以被集成到诸如微处理器的逻辑处理中。用于生成MIM电容器的处理适用于当前的逻辑处理技术。描述和要求保护其他实施例。

113. 发明申请

US20060262610A1 Reducing power consumption in integrated circuits 有权
标题翻译：降低集成电路的功耗
公开(公告)号：US20060262610A1
公开(公告)日：2006-11-23
申请号：US11134450
申请日：2005-05-23
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C8/12
摘要： A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
摘要翻译：提供了一种降低集成存储器件功耗的方法和装置。存储单元组可以通过相应的“睡眠”晶体管单独地进入“睡眠”模式。

114. 发明申请

US20060067152A1 Crosspoint memory array utilizing one time programmable antifuse cells 有权
公开(公告)号：US20060067152A1
公开(公告)日：2006-03-30
申请号：US10954537
申请日：2004-09-29
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G11C17/18 , G11C5/06
CPC分类号： G11C17/16
摘要： Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

115. 发明申请

US20060067133A1 Apparatus and method for a one-phase write to a one-transistor memory cell array 失效
标题翻译：用于单相写入单晶体管存储单元阵列的装置和方法
公开(公告)号：US20060067133A1
公开(公告)日：2006-03-30
申请号：US10956407
申请日：2004-09-30
申请人： Yibin Ye , Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Gerhard Schrom , Vivek De
发明人： Yibin Ye , Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Gerhard Schrom , Vivek De
IPC分类号： G11C7/10
CPC分类号： G11C11/404 , G11C2211/4016
摘要： A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.
摘要翻译：用于单相写入单晶体管存储单元阵列的方法和装置。在一个实施例中，该方法包括对存储器单元阵列的选定字线的单相写入。一旦选择了字线，逻辑零值被存储在存储单元阵列的选定字线的至少一个存储单元中。同时，逻辑0值存储在所选择的存储单元阵列的选定字线的至少一个存储单元中。描述和要求保护其他实施例。

116. 发明申请

US20060067109A1 SRAM CELL POWER REDUCTION CIRCUIT 有权
标题翻译： SRAM单元功率降低电路
公开(公告)号：US20060067109A1
公开(公告)日：2006-03-30
申请号：US10956195
申请日：2004-09-30
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen Tang , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , James Tschanz , Stephen Tang , Vivek De
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C11/413
摘要： A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.
摘要翻译：描述了一种方法，其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。电压超过另一个电压，运算放大器将驱动节点没有晶体管的帮助。电压有助于反馈回路在SRAM内的单元上建立一个压降。

117. 发明申请

US20060014331A1 Floating-body DRAM in tri-gate technology 有权
标题翻译：三门技术中的浮体DRAM
公开(公告)号：US20060014331A1
公开(公告)日：2006-01-19
申请号：US10879480
申请日：2004-06-30
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
摘要翻译：浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

118. 发明授权

US06903984B1 Floating-body DRAM using write word line for increased retention time 失效
标题翻译：使用写字线的浮体DRAM增加保留时间
公开(公告)号：US06903984B1
公开(公告)日：2005-06-07
申请号：US10748222
申请日：2003-12-31
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De
IPC分类号： G11C11/404 , G11C11/408 , H01L27/108 , H01L29/78 , G11C7/00
CPC分类号： H01L27/108 , G11C11/404 , G11C11/4085 , H01L29/7841
摘要： A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
摘要翻译： DRAM存储单元使用单个晶体管来执行常规单元的数据存储和切换功能。晶体管具有浮置通道体，其存储对应于两个数字数据值之一的电位。晶体管还包括连接到第一字线的栅极，连接到第二字线的漏极和连接到位线的源极。通过将单词和位线设置为特定的电压状态，通道体由于碰撞电离而存储数字一个电位，并且由于体对源结的正向偏置而存储数字零值。

119. 发明授权

US06801463B2 Method and apparatus for leakage compensation with full Vcc pre-charge 有权
标题翻译：具有全Vcc预充电的漏电补偿方法和装置
公开(公告)号：US06801463B2
公开(公告)日：2004-10-05
申请号：US10273627
申请日：2002-10-17
申请人： Muhammad M. Khellah , Yibin Ye , Dinesh Somasekhar , Vivek De
发明人： Muhammad M. Khellah , Yibin Ye , Dinesh Somasekhar , Vivek De
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： A leakage compensation approach enabling full VCC precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially a supply voltage level and a leakage compensation circuit supplies a first compensation current to a first one of the bit lines to substantially compensate for leakage current supplied by the first bit line during a memory access operation directed to one of the plurality of memory cells.
摘要翻译：一种允许全VCC预充电的漏电补偿方式。存储器单元阵列耦合在一对位线之间。预充电电路将该对位线预充电到基本上的电源电压电平，并且泄漏补偿电路向位线中的第一位提供第一补偿电流，以在存储器访问操作期间基本上补偿由第一位线提供的泄漏电流指向多个存储器单元中的一个。

120. 发明授权

US08640005B2 Method and apparatus for using cache memory in a system that supports a low power state 有权
标题翻译：在支持低功率状态的系统中使用高速缓冲存储器的方法和装置
公开(公告)号：US08640005B2
公开(公告)日：2014-01-28
申请号：US12785182
申请日：2010-05-21
申请人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.
摘要翻译：高速缓冲存储器系统使用具有低存储和复杂度开销的多位错误校正码（ECC）。在一个实施例中，纠错逻辑可以包括：第一纠错逻辑，用于确定存储在高速缓存存储器的高速缓存行中的数据中的错误数;以及第二纠错逻辑，用于从第一纠错逻辑接收数据如果错误的数量被确定为大于1，并且响应于数据的接收执行错误校正。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式