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111. 发明申请

US20050104210A1 Use of palladium in IC manufacturing with conductive polymer bump 审中-公开
标题翻译：在导电聚合物凸块的IC制造中使用钯
公开(公告)号：US20050104210A1
公开(公告)日：2005-05-19
申请号：US11008654
申请日：2004-12-09
申请人： Warren Farnworth , Salman Akram
发明人： Warren Farnworth , Salman Akram
IPC分类号： H01L21/288 , H01L21/48 , H01L21/56 , H01L21/60 , H01L23/485 , H01L23/498 , H05K3/24 , H05K3/32 , H01L21/44 , H01L23/48
CPC分类号： H05K3/321 , H01L21/288 , H01L21/4853 , H01L21/563 , H01L23/49811 , H01L23/49816 , H01L23/49894 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/11 , H01L2224/1132 , H01L2224/12 , H01L2224/13099 , H01L2224/1319 , H01L2224/16 , H01L2224/16225 , H01L2224/2919 , H01L2224/29298 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/12044 , H01L2924/14 , H05K3/244 , H05K2201/10674 , H05K2201/10977 , H05K2201/10984 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2924/00012
摘要： An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point. The present invention also relates to assemblies comprising one or more of these substrates.
摘要翻译：一种用于在钯镀层的接触点上形成具有钯金属层的衬底的装置和方法，该衬底在衬底的至少一个接触点上并且具有柔性导电聚合物凸点，优选两级环氧树脂。本发明还涉及包括一个或多个这些基底的组件。

112. 发明申请

US20050049751A1 Machine vision systems for use with programmable material consolidation apparatus and systems 审中-公开
标题翻译：机器视觉系统用于可编程材料合并装置和系统
公开(公告)号：US20050049751A1
公开(公告)日：2005-03-03
申请号：US10705727
申请日：2003-11-10
申请人： Warren Farnworth
发明人： Warren Farnworth
IPC分类号： B29C67/00 , G05B15/00
CPC分类号： B29C64/35 , B29C64/135 , B33Y30/00 , B33Y40/00 , B33Y50/02
摘要： A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.
摘要翻译：编程材料合并装置包括与所述至少一个制造位置相关联的至少一个制造位置和材料固结系统。至少一个制造位置可以被配置为接收一个或多个制造衬底，例如半导体衬底。具有可移动或位置固定的照相机的机器视觉系统可以与至少一个制造场所和材料合并系统相关联。清洁部件也可以与至少一个制造部位相关联。清洁部件可以与至少一个制造部位共享一个或多个元件，或者可以与其分开。编程材料合并装置还可以包括基板处理系统，其将制造基板放置在编程材料固结装置的适当位置。

113. 发明申请

US20050032387A1 Asymmetric plating 有权
标题翻译：不对称电镀
公开(公告)号：US20050032387A1
公开(公告)日：2005-02-10
申请号：US10930510
申请日：2004-08-31
申请人： Warren Farnworth , Joseph Lindgren
发明人： Warren Farnworth , Joseph Lindgren
IPC分类号： C25D3/12 , C25D5/02 , C25D7/12 , H01L21/288 , H01L21/60 , H01L23/485 , H05K3/24 , H05K3/40 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L24/12 , C25D3/12 , C25D5/02 , C25D7/12 , H01L21/288 , H01L24/11 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/13099 , H01L2224/16225 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/24 , H05K3/4007 , H01L2224/05655 , H01L2924/00014 , H01L2224/05124 , H01L2224/05147
摘要： A method and apparatus are disclosed for forming a tapered contact structure over a contact pad. The tapered contact structure may be used to securely anchor an overlying solder bump or solder ball. Additionally, the tapered contact structure allows the use of either larger contact pads or, alternately, allows a greater density of contact pads to be achieved on an integrated circuit substrate.
摘要翻译：公开了用于在接触垫上形成锥形接触结构的方法和装置。锥形接触结构可用于牢固地固定上覆焊料凸块或焊球。此外，锥形接触结构允许使用更大的接触焊盘，或者允许在集成电路基板上实现更大密度的接触焊盘。

114. 发明申请

US20050023621A1 Electrostatic discharge protection devices having transistors with textured surfaces 审中-公开
标题翻译：具有纹理表面的晶体管的静电放电保护器件
公开(公告)号：US20050023621A1
公开(公告)日：2005-02-03
申请号：US10930264
申请日：2004-08-31
申请人： Warren Farnworth , Lucien Bissey
发明人： Warren Farnworth , Lucien Bissey
IPC分类号： H01L21/285 , H01L21/336 , H01L21/768 , H01L27/02 , H01L29/06 , H01L23/62
CPC分类号： H01L29/66636 , H01L21/28512 , H01L21/76895 , H01L27/0251 , H01L29/0657 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device connects to a bonding pad and an internal circuit for protecting the internal circuit during an ESD event. The ESD protection device includes a transistor connected between the bonding pad and a supply node. The transistor includes a first doped region having a textured surface connected to the bonding pad, and a second doped region having a textured surface connected to the supply node.
摘要翻译：静电放电（ESD）保护器件连接到接合焊盘和内部电路，用于在ESD事件期间保护内部电路。 ESD保护器件包括连接在接合焊盘和电源节点之间的晶体管。晶体管包括具有连接到焊盘的纹理化表面的第一掺杂区域和具有连接到电源节点的纹理表面的第二掺杂区域。

115. 发明申请

US20050017358A1 Semiconductor component having conductors with wire bondable metalization layers 有权
标题翻译：具有可引线接合金属化层导体的半导体元件
公开(公告)号：US20050017358A1
公开(公告)日：2005-01-27
申请号：US10924010
申请日：2004-08-23
申请人： Warren Farnworth
发明人： Warren Farnworth
IPC分类号： H01L23/14 , H01L23/31 , H01L23/485 , H01L23/498 , H01L23/48
CPC分类号： H01L24/06 , H01L23/147 , H01L23/3114 , H01L23/4951 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/48 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05083 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/11 , H01L2224/1134 , H01L2224/114 , H01L2224/116 , H01L2224/13 , H01L2224/1308 , H01L2224/13082 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/32245 , H01L2224/45099 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48477 , H01L2224/73215 , H01L2224/85051 , H01L2224/85399 , H01L2225/0651 , H01L2225/06572 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/01065 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/30105 , H01L2224/05155 , H01L2224/05144 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor component includes a semiconductor die, a low k polymer layer on the die and redistribution conductors on the polymer layer. The component also includes bonding pads on the conductors with a metal stack construction that includes a conductive layer, a barrier/adhesion layer and a non-oxidizing layer. The bonding pads facilitate wire bonding to the component and the formation of reliable wire bonds on the component. A method for fabricating the component includes the steps of forming the conductors and bonding pads using electroless deposition. The component can be used to fabricate electronic assemblies such as modules, packages and printed circuit boards.
摘要翻译：半导体部件包括半导体管芯，管芯上的低k聚合物层和聚合物层上的再分布导体。该部件还包括具有金属堆叠结构的导体上的接合焊盘，其包括导电层，阻挡层/粘合层和非氧化层。接合焊盘有助于引线接合到部件上并在部件上形成可靠的引线接合。制造该部件的方法包括以下步骤：使用无电沉积形成导体和接合焊盘。该组件可用于制造诸如模块，封装和印刷电路板的电子组件。

116. 发明授权

US06777261B2 Method and apparatus for a semiconductor package for vertical surface mounting 失效
标题翻译：用于垂直表面安装的半导体封装的方法和装置
公开(公告)号：US06777261B2
公开(公告)日：2004-08-17
申请号：US10304911
申请日：2002-11-26
申请人： Warren Farnworth , Larry Kinsman , Walter Moden
发明人： Warren Farnworth , Larry Kinsman , Walter Moden
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L23/3171 , H01L23/528 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175 , H01L2225/06527 , H01L2225/06551 , H01L2225/06575 , H01L2225/06582 , H01L2225/06593 , H01L2924/30107 , H01L2924/00
摘要： A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end. The present invention contemplates wire bonding and encapsulation of individual die as well as multiple die on a single wafer.
摘要翻译：一种用于封装半导体器件的方法包括将多个引线引线连接到半导体器件上的对应的多个电连接焊盘，覆盖半导体器件的至少一部分以及每个引线的至少一部分具有封装并且去除所述封装材料的一部分和所述导线引线中的每一个的一部分以形成封装的半导体器件，其中所述引线中的每一个仅在一端具有暴露部分。本发明还包括具有集成电路器件的封装半导体器件，该集成电路器件具有多个电连接焊盘，耦合到多个电连接焊盘的多个引线引线以及覆盖该集成电路的至少一部分的封装材料的覆盖物装置并且覆盖每个导线，其中每个导线具有暴露端。本发明设想在单个晶片上引线接合和封装单个管芯以及多个管芯。

117. 发明授权

US06673649B1 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages 有权
公开(公告)号：US06673649B1
公开(公告)日：2004-01-06
申请号：US10190019
申请日：2002-07-05
申请人： William Mark Hiatt , Warren Farnworth
发明人： William Mark Hiatt , Warren Farnworth
IPC分类号： H01L2100
CPC分类号： H01L23/3114 , H01L21/563 , H01L23/3107 , H01L23/3157 , H01L23/467 , H01L23/473 , H01L24/29 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/10126 , H01L2224/13022 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/83191 , H01L2224/83192 , H01L2224/83194 , H01L2224/92125 , H01L2924/00014 , H01L2924/01005 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/00 , H01L2224/05599
摘要： A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.

118. 发明申请

US20080102552A1 WAFER LEVEL METHOD OF LOCATING FOCAL PLANE OF IMAGER DEVICES 有权
标题翻译：定位成像装置的焦平面的水平方法
公开(公告)号：US20080102552A1
公开(公告)日：2008-05-01
申请号：US11554243
申请日：2006-10-30
申请人： Warren Farnworth
发明人： Warren Farnworth
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14685 , H01L27/14689 , H01L2224/48091 , H01L2924/15174 , H04N5/2257 , H01L2924/00014
摘要： A method is disclosed which includes providing an imager substrate comprised of at least one imager device, providing a transparent substrate, forming a plurality of standoff structures on one of the imager substrate and the transparent substrate, the standoff structures having a width, forming an adhesive material having an initial thickness on a surface on at least one of the standoff structures, the adhesive material having an initial width that is less than the width of the standoff structures, and urging one of the imager substrate and the transparent substrate toward the other until such time as the imager substrate and the transparent substrate are in proper focal position relative to one another, the urging causing the initial thickness of the adhesive material to be reduced to a final thickness that is less than the initial thickness.
摘要翻译：公开了一种方法，其包括提供由至少一个成像器件构成的成像器衬底，提供透明衬底，在成像器衬底和透明衬底之一上形成多个间隔结构，所述间隔结构具有宽度，形成粘合剂在至少一个支座结构上的表面上具有初始厚度的材料，所述粘合材料具有小于所述支座结构的宽度的初始宽度，并且将所述成像器基板和所述透明基板中的一个朝向另一个，直到像成像器基板和透明基板相对于彼此处于适当的焦点位置的时间，使粘合剂材料的初始厚度减小到小于初始厚度的最终厚度的推动。

119. 发明申请

US20080060193A1 METHODS OF FABRICATING SUBSTRATES INCLUDING AT LEAST ONE CONDUCTIVE VIA 有权
标题翻译：制造基板的方法，包括至少一个导电的基板
公开(公告)号：US20080060193A1
公开(公告)日：2008-03-13
申请号：US11941358
申请日：2007-11-16
申请人： Warren Farnworth , Steven McDonald , Nishant Sinha , William Hiatt
发明人： Warren Farnworth , Steven McDonald , Nishant Sinha , William Hiatt
IPC分类号： H05K3/06 , H05K3/02
CPC分类号： H05K3/426 , H01L21/486 , H01L23/147 , H01L23/15 , H01L23/49816 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H05K3/062 , H05K3/108 , H05K3/244 , H05K2203/072 , Y10T29/49117 , Y10T29/49123 , Y10T29/49126 , Y10T29/49147 , Y10T29/49155 , Y10T29/49156 , Y10T29/4916 , Y10T29/49163 , Y10T29/49165 , Y10T29/49167 , H01L2924/00
摘要： A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.
摘要翻译：公开了一种制造衬底的方法。孔径形成在基板坯件中。导电层形成在基板的相对表面上以及孔内。通过掩模和蚀刻在一个或两个相对的表面上限定导电元件。可以使用附加的导电材料层来提供用于导电元件的阻挡层和贵金属盖。本发明的方法可用于制造用于封装半导体器件或测试基板的插入器。还公开了底物前体结构。

120. 发明申请

US20070075722A1 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
公开(公告)号：US20070075722A1
公开(公告)日：2007-04-05
申请号：US11607162
申请日：2006-12-01
申请人： Warren Farnworth , William Waller , Leland Nevill , Raymond Beffa , Eugene Cloud
发明人： Warren Farnworth , William Waller , Leland Nevill , Raymond Beffa , Eugene Cloud
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01R31/2884
摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

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