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111. 发明申请

US20120175731A1 SEMICONDUCTOR STRUCTURE WITH PASSIVE ELEMENT NETWORK AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有被动元件网络的半导体结构及其制造方法
公开(公告)号：US20120175731A1
公开(公告)日：2012-07-12
申请号：US13338087
申请日：2011-12-27
申请人： Chien-Hua Chen , Teck-Chong Lee , Hsu-Chiang Shih , Meng-Wei Hsieh
发明人： Chien-Hua Chen , Teck-Chong Lee , Hsu-Chiang Shih , Meng-Wei Hsieh
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L27/016 , H01L21/76898 , H01L23/147 , H01L23/49822 , H01L23/49827 , H01L23/5227 , H01L23/5228 , H01L23/60 , H01L23/64 , H01L25/0657 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2224/16 , H01L2225/06517 , H01L2225/06572 , H01L2924/1461 , H01L2924/00
摘要： The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor.
摘要翻译：本发明涉及一种具有集成无源网络的半导体结构及其制造方法。半导体结构包括可以是插入件的衬底。衬底可以包括多个导电通孔。在各种实施例中，衬底包括设置在其上的电介质层，电介质层具有形成直孔的开口，允许无源网络和导电通孔之间的电连接。无源网络包括一系列图案化的电介质层和导电层，形成无源电子元件。在一个实施例中，无源器件包括耦合到一对电感器的公共电阻器，每个电感器耦合到电容器。在另一个实施例中，无源器件包括电阻器和电感器，它们彼此电连接，电感器的底表面与电阻器的底表面共面。

112. 发明申请

US20120153441A1 OVERLAY MARK ENHANCEMENT FEATURE 有权
标题翻译： OVERLAY MARK ENHANCEMENT功能
公开(公告)号：US20120153441A1
公开(公告)日：2012-06-21
申请号：US13408618
申请日：2012-02-29
申请人： Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
发明人： Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
IPC分类号： H01L29/06
CPC分类号： G03F7/70633 , G03F9/7076 , G03F9/7084 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.
摘要翻译：集成电路器件包括具有器件区域和对准区域的半导体衬底。第一材料层设置在半导体衬底上，并且包括器件区域中的器件特征和对准区域中的虚拟特征。虚拟特征的尺寸小于对准检测器的尺寸。第二材料层设置在半导体衬底上，并且包括对准区域中的对准特征。布置在虚拟特征上的对准特征。

113. 发明授权

US08148232B2 Overlay mark enhancement feature 有权
标题翻译：叠加标记增强功能
公开(公告)号：US08148232B2
公开(公告)日：2012-04-03
申请号：US12854660
申请日：2010-08-11
申请人： Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
发明人： Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
IPC分类号： H01L21/70
CPC分类号： G03F7/70633 , G03F9/7076 , G03F9/7084 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatuses for alignment are disclosed. An exemplary method includes providing a substrate having a device region and an alignment region; forming a first material layer over the substrate; forming a device feature and a dummy feature in the first material layer, wherein the device feature is formed in the device region and the dummy feature is formed in the alignment region; forming a second material layer over the first material layer; and forming an alignment feature in the second material layer, the alignment feature being disposed over the dummy feature in the alignment region. The device feature has a first dimension and the dummy feature has a second dimension, the second dimension being less than a resolution of an alignment mark detector.
摘要翻译：公开了用于对准的方法和装置。一种示例性方法包括提供具有器件区域和对准区域的衬底; 在所述衬底上形成第一材料层; 在所述第一材料层中形成器件特征和虚拟特征，其中所述器件特征形成在所述器件区域中，并且所述伪特征形成在所述对准区域中; 在所述第一材料层上形成第二材料层; 以及在所述第二材料层中形成对准特征，所述对准特征被布置在所述对准区域中的所述虚拟特征之上。设备特征具有第一维度，虚拟特征具有第二维度，第二维度小于对准标记检测器的分辨率。

114. 发明申请

US20140015122A1 Method of Forming Post Passivation Interconnects 有权
标题翻译：形成后钝化互连的方法
公开(公告)号：US20140015122A1
公开(公告)日：2014-01-16
申请号：US13546300
申请日：2012-07-11
申请人： Meng-Wei Chou , Hung-Jui Kuo , Ming-Che Ho , Chung-Shi Liu
发明人： Meng-Wei Chou , Hung-Jui Kuo , Ming-Che Ho , Chung-Shi Liu
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L23/525 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02331 , H01L2224/03464 , H01L2224/0361 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05184 , H01L2224/05548 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2924/00014 , H01L2924/12042 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure.
摘要翻译：形成后钝化互连的方法包括在衬底上形成钝化层，其中金属焊盘嵌入钝化层中，在钝化层上沉积第一介电层，将第一图案化工艺应用于第一介电层以形成第一开口，在第一开口上形成第一种子层，用导电材料填充第一开口，在第一介电层上沉积第二介电层，向第二介电层施加第二图案化工艺以形成第二开口，形成在第二开口上方的凸块下金属化结构，并且在凸块下金属化结构之上安装互连凸块。

115. 发明授权

US08564374B2 Oscillator calibration apparatus and oscillator calibration method 有权
标题翻译：振荡器校准装置和振荡器校准方法
公开(公告)号：US08564374B2
公开(公告)日：2013-10-22
申请号：US13252171
申请日：2011-10-03
申请人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
发明人： Chun-Yu Chiu , Yaw-Guang Chang , Meng-Wei Shen
IPC分类号： H03L7/06 , H03L7/183
CPC分类号： H03L7/097 , H03L7/091
摘要： An oscillator calibration apparatus includes a counter, a comparator and an adjusting unit. The counter is utilized for receiving a first clock signal and a second clock signal, and utilizing the first clock signal to sample the second clock signal to generate at least one counting value, where the first clock signal is generated from a first oscillator, and the second clock signal is generated from a second oscillator different from the first oscillator; the comparator is coupled to the counter, and is utilized for comparing the counting value with a predetermined value to generate at least one calibration signal; and the adjusting unit is coupled to the comparator, and is utilized for adjusting a frequency of the second oscillator according to the calibration signal.
摘要翻译：振荡器校准装置包括计数器，比较器和调整单元。该计数器用于接收第一时钟信号和第二时钟信号，并利用第一时钟信号对第二时钟信号进行采样以产生至少一个计数值，其中第一时钟信号从第一振荡器产生，从与第一振荡器不同的第二振荡器产生第二时钟信号; 比较器被耦合到计数器，并且用于将计数值与预定值进行比较以产生至少一个校准信号; 并且所述调整单元耦合到所述比较器，并且用于根据所述校准信号调整所述第二振荡器的频率。

116. 发明授权

US08524559B2 Manufacturing method of power transistor device 有权
标题翻译：功率晶体管器件的制造方法
公开(公告)号：US08524559B2
公开(公告)日：2013-09-03
申请号：US13533957
申请日：2012-06-26
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Main-Gwo Chen , Chia-Hao Chang , Chia-Wei Chen
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Main-Gwo Chen , Chia-Hao Chang , Chia-Wei Chen
IPC分类号： H01L21/336 , H01L21/22 , H01L21/38
CPC分类号： H01L29/7827 , H01L21/2255 , H01L29/0634 , H01L29/0653 , H01L29/0869 , H01L29/0886 , H01L29/41766 , H01L29/41775 , H01L29/4236 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
摘要翻译：本发明提供一种功率晶体管器件，其包括衬底，外延层，掺杂剂源层，掺杂漏极区，第一绝缘层，栅极结构，第二绝缘层，掺杂源极区和金属层。衬底，掺杂漏极区域和掺杂源极区域具有第一导电类型，而外延层具有第二导电类型。外延层形成在衬底上并且具有穿过外延层的至少一个通孔。第一绝缘层，栅极结构和第二绝缘层依次形成在通孔中的基板上。掺杂漏极区域和掺杂源极区域形成在通孔一侧的外延层中。金属层形成在外延层上并延伸到通孔中以与掺杂源极区接触。

117. 发明授权

US08466051B2 Method for fabricating Schottky device 有权
标题翻译：制造肖特基器件的方法
公开(公告)号：US08466051B2
公开(公告)日：2013-06-18
申请号：US13338256
申请日：2011-12-28
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Main-Gwo Chen , Chia-Hao Chang , Chia-Wei Chen
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Main-Gwo Chen , Chia-Hao Chang , Chia-Wei Chen
IPC分类号： H01L21/338 , H01L29/812
CPC分类号： H01L21/22 , H01L21/2254 , H01L21/2256 , H01L21/2257 , H01L21/2652 , H01L21/28 , H01L29/66143 , H01L29/872
摘要： A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer.
摘要翻译：制造肖特基器件的方法包括以下顺序。首先，提供具有第一导电类型的衬底，并且在衬底上生长具有第一导电类型的外延层。然后，在外延层上形成图案化的介电层，在外延层的表面上形成金属硅化物层。在金属硅化物层上形成具有第二导电类型的掺杂剂源层，随后施加热驱动工艺以将掺杂剂源层内的掺杂剂扩散到外延层中。最后，在金属硅化物层上形成导电层。

118. 发明授权

US08455982B2 Overlay mark enhancement feature 有权
标题翻译：叠加标记增强功能
公开(公告)号：US08455982B2
公开(公告)日：2013-06-04
申请号：US13408618
申请日：2012-02-29
申请人： Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
发明人： Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
IPC分类号： H01L29/06
CPC分类号： G03F7/70633 , G03F9/7076 , G03F9/7084 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.
摘要翻译：集成电路器件包括具有器件区域和对准区域的半导体衬底。第一材料层设置在半导体衬底上，并且包括器件区域中的器件特征和对准区域中的虚拟特征。虚拟特征的尺寸小于对准检测器的尺寸。第二材料层设置在半导体衬底上，并且包括对准区域中的对准特征。布置在虚拟特征上的对准特征。

119. 发明授权

US08455946B2 Lateral stack-type super junction power semiconductor device 有权
标题翻译：横向叠层型超结功率半导体器件
公开(公告)号：US08455946B2
公开(公告)日：2013-06-04
申请号：US13337274
申请日：2011-12-26
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L21/2254 , H01L21/26586 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66696 , H01L29/66704 , H01L29/7825
摘要： A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure.
摘要翻译：横向叠层型超结功率半导体器件包括半导体衬底; 半导体衬底上的外延堆叠结构，具有第一外延层和第二外延层; 漏极结构，其嵌入所述外延堆叠结构中并且沿着第一方向延伸; 嵌入在所述外延堆叠结构中并沿着所述第一方向以分段方式布置的多个栅极结构; 所述多个门结构之间的源结构; 以及包围源结构的离子阱。

120. 发明申请

US20130082324A1 LATERAL STACK-TYPE SUPER JUNCTION POWER SEMICONDUCTOR DEVICE 有权
标题翻译：横向堆叠式超级功率半导体器件
公开(公告)号：US20130082324A1
公开(公告)日：2013-04-04
申请号：US13337274
申请日：2011-12-26
申请人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
发明人： Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Chia-Hao Chang
IPC分类号： H01L27/088
CPC分类号： H01L29/0634 , H01L21/2254 , H01L21/26586 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66696 , H01L29/66704 , H01L29/7825
摘要： A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure.
摘要翻译：横向叠层型超结功率半导体器件包括半导体衬底; 半导体衬底上的外延堆叠结构，具有第一外延层和第二外延层; 漏极结构，其嵌入所述外延堆叠结构中并且沿着第一方向延伸; 嵌入在所述外延堆叠结构中并沿着所述第一方向以分段方式布置的多个栅极结构; 所述多个门结构之间的源结构; 以及包围源结构的离子阱。

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