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111. 发明专利

JP5059328B2 Method and apparatus for controlling an output power out of the switching power supply 有权
公开(公告)号：JP5059328B2
公开(公告)日：2012-10-24
申请号：JP2006007124
申请日：2006-01-16
申请人：パワー・インテグレーションズ・インコーポレーテッド
发明人：スティーブン・ダブリュ・ホーリー
IPC分类号： H02M3/28
CPC分类号： H02M1/32 , H02M3/156 , H02M3/33507

112. 发明专利

JP4928180B2 A method and apparatus for limiting the maximum switch current in the switch of a switching power supply 有权
公开(公告)号：JP4928180B2
公开(公告)日：2012-05-09
申请号：JP2006189048
申请日：2006-07-10
申请人：パワー・インテグレーションズ・インコーポレーテッド
发明人：デレック・ジェイ・クローズ
IPC分类号： H02M3/28
CPC分类号： H02M3/33507 , H02M1/32 , H02M2001/0009 , H02M2001/0038 , Y10S323/908

113. 发明专利

JP4903601B2 A method and apparatus for inrush current limiting circuit 有权
公开(公告)号：JP4903601B2
公开(公告)日：2012-03-28
申请号：JP2007043475
申请日：2007-02-23
申请人：パワー・インテグレーションズ・インコーポレーテッド
发明人：ロバート・ジェイ・メイイェル
IPC分类号： G05F1/10
CPC分类号： H02H9/001

114. 发明专利

JP4898619B2 Gate etching method for high-voltage fet 有权
公开(公告)号：JP4898619B2
公开(公告)日：2012-03-21
申请号：JP2007258532
申请日：2007-10-02
申请人：パワー・インテグレーションズ・インコーポレーテッド
发明人：レイディズニードナルド
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/407 , H01L21/311 , H01L29/41741 , H01L29/66734 , H01L29/7813
摘要： A method, in one embodiment, includes etching first and second dielectric regions (15a,15b) in a substantially isotropic manner through first and second openings (22a,22b) of a mask layer (21) to create first and second trenches (24a,24b). The first and second dielectric regions are disposed on opposite sides of a mesa (14) of semiconductor material, the mesa having first and second sidewalls (19a,19b) that respectively adjoin the first and second dielectric regions. The first and second dielectric regions in the first and second trenches are then etched in a substantially isotropic manner to expose the first and second sidewalls. A gate oxide (33a,33b) is formed on the first and second sidewalls of the mesa.

116. 发明专利

JP2011159987A Method for fabricating high-voltage transistor with multilayer extended drain structure 有权
标题翻译：用于制造具有多层延伸排水结构的高压晶体管的方法
公开(公告)号：JP2011159987A
公开(公告)日：2011-08-18
申请号：JP2011067774
申请日：2011-03-25
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： DISNEY DONALD RAY
IPC分类号： H01L21/336 , H01L29/786 , H01L27/04 , H01L29/06 , H01L29/40 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/78
CPC分类号： H01L29/407 , H01L29/0653 , H01L29/0878 , H01L29/402 , H01L29/41741 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/66666 , H01L29/66681 , H01L29/66704 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7813 , H01L29/7824 , H01L29/7825 , H01L29/7828 , Y10S438/925
摘要： PROBLEM TO BE SOLVED: To provide a method for fabricating a high-voltage transistor with an extended drain region. SOLUTION: A method for fabricating a high-voltage transistor with an extended drain region comprises: forming an epitaxial layer on a substrate, both the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种制造具有延伸漏极区域的高压晶体管的方法。解决方案：一种用于制造具有延伸漏极区的高电压晶体管的方法包括：在衬底上形成外延层，外延层和衬底都是第一导电类型; 然后蚀刻外延层以形成限定外延层的第一和第二侧壁部分的一对隔开的沟槽。形成介电层，其部分地填充每个沟槽，覆盖第一和第二侧壁部分。然后用导电材料填充沟槽的剩余部分，以形成与衬底和外延层绝缘的第一和第二场板构件。版权所有（C）2011，JPO＆INPIT

117. 发明专利

JP4744057B2 High voltage lateral transistor having a multi-layered extended drain structure 有权
公开(公告)号：JP4744057B2
公开(公告)日：2011-08-10
申请号：JP2002258263
申请日：2002-07-31
申请人：パワー・インテグレーションズ・インコーポレーテッド
发明人：レイディズニードナルド , ダーウィッシュモハメド
IPC分类号： H01L29/78 , H01L29/786 , H01L21/336 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/861
CPC分类号： H01L29/7824 , H01L29/0653 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/7802 , H01L29/7813 , H01L29/7825 , H01L29/86 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： A high-voltage semiconductor structure (40) with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions (42) separated from field plate members (44) by one or more dielectric layers (49). With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations.

118. 发明专利

JP2010183828A Control circuit, and method for controlling output of power converter 审中-公开
标题翻译：控制电路及控制功率转换器输出的方法
公开(公告)号：JP2010183828A
公开(公告)日：2010-08-19
申请号：JP2010022902
申请日：2010-02-04
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： ALEX B DJENGUERIAN , LUND LEIF
IPC分类号： H02M3/28 , H02M1/00
CPC分类号： H02M3/33523 , H02M1/08 , H02M3/33507 , H02M2001/0009 , H02M2001/0032 , Y02B70/16 , Y10T307/406
摘要： PROBLEM TO BE SOLVED: To provide a method and apparatus for achieving a control circuit for reducing energy consumption of a power converter under the conditions of a light or no load using an unregulated dormant mode. SOLUTION: A control circuit 115 includes a drive signal generator coupled to generate a drive signal for controlling switching of a power switch 105 to be coupled to the control circuit and regulate a flow of energy to a power converter output in response to an energy requirement of one or more loads to be coupled to the power converter output. An unregulated dormant mode control circuit is included and is coupled to render the drive signal generator dormant, thereby ceasing the regulation of the flow of energy to the power converter output by the drive signal generator when the energy requirement of the one or more loads falls below a threshold for more than a first period of time. The drive signal generator is coupled to be unresponsive to changes in the energy requirements of the one or more loads when dormant. The unregulated dormant mode control circuit is coupled to raise the power of the drive signal generator after a second period of time has elapsed. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种用于在使用未调节的休眠模式的轻载或无负载的条件下实现用于降低功率转换器的能量消耗的控制电路的方法和装置。解决方案：控制电路115包括驱动信号发生器，其耦合以产生用于控制要耦合到控制电路的电源开关105的开关的驱动信号，并响应于一个控制电路调节到功率转换器输出的能量流要耦合到功率转换器输出的一个或多个负载的能量需求。一个不受监管的休眠模式控制电路被包括并被耦合以使得驱动信号发生器处于休眠状态，从而当一个或多个负载的能量需求低于下限时停止对由驱动信号发生器输出的功率流的调节超过第一个时间段的阈值。当休眠时，驱动信号发生器被耦合以对一个或多个负载的能量需求的变化无响应。未调节的休眠模式控制电路被耦合以在经过第二时间段之后提高驱动信号发生器的功率。版权所有（C）2010，JPO＆INPIT

119. 发明专利

JP2010154750A Method and apparatus for fault condition protection of switched mode power supply 有权
标题翻译：开关电源故障状态保护方法与装置
公开(公告)号：JP2010154750A
公开(公告)日：2010-07-08
申请号：JP2010075707
申请日：2010-03-29
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： BALAKRISHNAN BALU
IPC分类号： H02M3/28 , H02M1/00 , H02M1/32 , H02M1/36
CPC分类号： H02M1/32 , H02H3/06 , H02H3/087 , H02M1/36
摘要： PROBLEM TO BE SOLVED: To provide a method and arrangement for fault condition protection of a switch mode power supply.
SOLUTION: A power supply circuit is included that has an automatic restart function for turning on of the power supply repeatedly under fault conditions. One or a plurality of off-times following the detection of a fault condition is smaller than the subsequent off-times.
COPYRIGHT: (C)2010,JPO&INPIT

120. 发明专利

JP2010153864A Power transistor device manufactured on semiconductor die 审中-公开
标题翻译：功率晶体管器件制造在半导体器件上
公开(公告)号：JP2010153864A
公开(公告)日：2010-07-08
申请号：JP2009287436
申请日：2009-12-18
申请人： Power Integrations Inc , パワー・インテグレーションズ・インコーポレーテッド
发明人： PARTHASARATHY VIJAY , BANERJEE SUJIT
IPC分类号： H01L29/06 , H01L21/28 , H01L29/41 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7397 , H01L29/407 , H01L29/66348
摘要： PROBLEM TO BE SOLVED: To provide a power semiconductor device structure, and to provide a process for manufacturing a high-voltage transistor. SOLUTION: A power transistor device includes a substrate and the substrate forms a PN junction with a buffer layer that overlaps thereon. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing sidewall portions in the transverse direction in the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供功率半导体器件结构，并提供制造高压晶体管的工艺。解决方案：功率晶体管器件包括衬底，并且衬底与其上重叠的缓冲层形成PN结。功率晶体管器件还包括第一区域，与缓冲层的顶表面相邻的漂移区域和主体区域。身体区域将第一区域与漂移区域分开。第一和第二电介质区域在漂移区域中分别邻接在横向方向上的相对的侧壁部分。电介质区域至少在身体区域的正下方沿垂直方向向下延伸至少至缓冲层。第一和第二场板分别设置在第一和第二电介质区域中。控制正向传导的沟槽栅极设置在与身体区域相邻并绝缘的电介质区域的上方。版权所有（C）2010，JPO＆INPIT

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