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101. 发明授权

US10037294B2 Semiconductor device, electronic component, and electronic device 有权
公开(公告)号：US10037294B2
公开(公告)日：2018-07-31
申请号：US15590406
申请日：2017-05-09
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya Onuki , Wataru Uesugi
IPC分类号： G11C11/4091 , G06F13/40 , G11C15/04 , G06F13/10 , G06F13/42 , G06F15/80 , G06F12/02 , G06F12/0831 , G11C14/00
CPC分类号： G06F13/40 , G06F12/0246 , G06F12/0831 , G06F13/10 , G06F13/4256 , G06F15/80 , G11C5/025 , G11C7/1039 , G11C11/4091 , G11C14/0027 , G11C14/0036 , G11C14/0054 , G11C14/0072 , G11C14/0081 , G11C15/04 , Y02D10/14 , Y02D10/151
摘要： A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.

102. 发明授权

US09899085B1 Non-volatile FeSRAM cell capable of non-destructive read operations 有权
公开(公告)号：US09899085B1
公开(公告)日：2018-02-20
申请号：US15393585
申请日：2016-12-29
申请人： AUCMOS Technologies USA, Inc.
发明人： Tianhong Yan
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/0072 , G11C11/22 , G11C11/221
摘要： A FeSRAM cell includes (a) first and second inverters between a power supply voltage and a ground reference cross-coupled to each other, the first and second cross-coupled inverters providing first and second data terminals; (b) first and second select transistors respectively coupled to the first and second data terminals to control access to the first second data terminals; and (c) first and second ferroelectric capacitors coupled between a first plate line and respectively the first and second data terminals, the first plate line receiving a negative programming voltage having a magnitude greater than the power supply voltage to allow programming one of the first and second ferroelectric capacitors into a first non-volatile programmed state.

103. 发明申请

US20170337149A1 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20170337149A1
公开(公告)日：2017-11-23
申请号：US15590406
申请日：2017-05-09
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya ONUKI , Wataru UESUGI
IPC分类号： G06F13/40 , G06F13/10 , G06F15/80 , G11C15/04 , G06F12/02 , G06F12/0831 , G06F13/42 , G11C14/00
CPC分类号： G06F13/40 , G06F12/0246 , G06F12/0831 , G06F13/10 , G06F13/4256 , G06F15/80 , G11C5/025 , G11C7/1039 , G11C11/4091 , G11C14/0027 , G11C14/0036 , G11C14/0054 , G11C14/0072 , G11C14/0081 , G11C15/04
摘要： A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.

104. 发明授权

US09514816B1 Non-volatile static RAM and method of operation thereof 有权
标题翻译：非易失性静态RAM及其操作方法
公开(公告)号：US09514816B1
公开(公告)日：2016-12-06
申请号：US14864594
申请日：2015-09-24
申请人： Cypress Semiconductor Corporation
发明人： Jayant Ashokkumar , Donald J. Verhaeghe , Alan D DeVilbiss , Qidao Li , Fan Chu , Judith Allen
IPC分类号： G11C11/00 , G11C14/00 , G11C11/22 , G11C11/419
CPC分类号： G11C14/0072 , G11C11/221 , G11C11/2273 , G11C11/419
摘要： A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.
摘要翻译：一种存储器件和阵列，其包括耦合到诸如铁电RAM（F-RAM）电路的非易失性电路的静态随机存取存储器（SRAM）电路，其中F-RAM电路存储来自在断电期间的SRAM电路中，当操作电源恢复时，F-RAM电路进一步耦合到位线以输出存储在F-RAM电路中的数据位。

105. 发明申请

US20160217861A1 Split Voltage Non-Volatile Latch Cell 有权
标题翻译：分离电压非易失性锁存器
公开(公告)号：US20160217861A1
公开(公告)日：2016-07-28
申请号：US14858813
申请日：2015-09-18
申请人： Cypress Semiconductor Corporation
发明人： Jayant Ashokkumar , Vijay Raghavan , Venkatraman Prabhakar , Swatilekha Saha
IPC分类号： G11C16/14 , G11C14/00 , G11C11/22 , G11C16/04
CPC分类号： G11C16/14 , G11C11/2275 , G11C14/00 , G11C14/0063 , G11C14/0072 , G11C16/0408 , G11C16/0466 , G11C16/0483
摘要： A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.
摘要翻译：提供包括非易失性锁存（NVL）单元阵列的存储器及其操作方法。在一个实施例中，每个NVL单元包括非易失性部分和易失性部分。非易失性部分包括第一非易失性存储器（NVM）器件和串联耦合在第一输出节点和位线真之间的第一非易失性存储器（NVM）器件和第一通过栅极晶体管，以及串联耦合的第二NVM器件和第二通过栅极晶体管第二输出节点和位线补码。易失性部分包括交叉耦合的第一和第二场效应晶体管（FET），耦合在电源电压（VPWR）和第一输出节点之间的第一FET以及耦合在VPWR和第二输出节点之间的第二FET。第一FET的栅极耦合到第二输出节点，并且第二FET的栅极耦合到第一输出节点。

106. 发明申请

US20160071587A1 C-ELEMENT WITH NON-VOLATILE BACK-UP 有权
标题翻译：具有非挥发性备份的C元素
公开(公告)号：US20160071587A1
公开(公告)日：2016-03-10
申请号：US14845213
申请日：2015-09-03
申请人： Commissariat à I`énergie atomique et aux énergies alternatives , Centre National de la Recherche Scientifique
发明人： Grégory Di Pendina , Edith Beigne , Eldar Zianbetov
IPC分类号： G11C13/00 , G11C11/22 , G11C11/16
CPC分类号： G11C13/0069 , G11C11/14 , G11C11/1675 , G11C11/22 , G11C11/2275 , G11C13/0004 , G11C14/0072 , G11C14/0081 , G11C14/009 , H03K19/01707 , H03K19/018585 , H03K19/20
摘要： The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes ( Q, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node ( Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (Rmin, Rmax), wherein a second terminal of the first resistive element (202) is coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).
摘要翻译：本发明涉及一种电路，包括：具有第一和第二输入节点的C元件和交叉耦合在第一和第二互补存储节点（Q，Z）之间的第一和第二反相器（110,112），第二存储节点（Z）形成C元件的输出节点; 和非易失性存储器，包括：具有耦合到所述第一存储节点（Q）的第一端子的第一电阻元件（202）。具有耦合到第二存储节点（Z）的第一端子的第二电阻元件（204），所述第一和第二电阻元件中的至少一个可编程为具有至少两个电阻状态（Rmin，Rmax）中的至少一个，其中a 第一电阻元件（202）的第二端子经由第一晶体管（210）耦合到第二电阻元件（204）的第二端子; 和控制电路（232）。

107. 发明授权

US08804403B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08804403B2
公开(公告)日：2014-08-12
申请号：US13969221
申请日：2013-08-16
申请人： Kabushiki Kaisha Toshiba
发明人： Keiichi Kushida
IPC分类号： G11C14/00
CPC分类号： G11C13/004 , G11C8/16 , G11C13/0069 , G11C14/0072 , G11C14/0081 , G11C14/009 , G11C2013/0073
摘要： According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.
摘要翻译：根据一个实施例，提供了一种包括存储单元的半导体存储器件。存储单元包括第一驱动晶体管，第一负载晶体管，第一读传输晶体管，第一写传输晶体管，第二驱动晶体管，第二负载晶体管，第二读传输晶体管，第二写传输晶体管和一或更多的可变电阻元件。一个或多个可变电阻元件具有根据施加到两个端子的偏压的方向而变化的电阻。一个或多个可变电阻元件被布置在第一存储节点和第一写入传输晶体管之间的部分中的至少一个以及第二存储节点和第二写入传输晶体管之间的部分中的至少一个中。

108. 发明申请

US20130247057A1 MULTI-TASK PROCESSING APPARATUS 审中-公开
标题翻译：多任务处理设备
公开(公告)号：US20130247057A1
公开(公告)日：2013-09-19
申请号：US13796197
申请日：2013-03-12
申请人： ROHM CO., LTD.
发明人： Yoshikazu Fujimori , Hiromitsu Kimura
IPC分类号： G06F9/48
CPC分类号： G06F9/4806 , G11C11/005 , G11C14/0072
摘要： A multi-task processing apparatus includes a sequencer for switching and processing multiple task data; a memory for storing the task data, wherein the memory stores/reads the task data between a volatile memory cell and a plurality of associated non-volatile memory cells when the task data is switched.
摘要翻译：多任务处理装置包括用于切换和处理多个任务数据的定序器; 用于存储任务数据的存储器，其中当所述任务数据被切换时，所述存储器在易失性存储器单元和多个相关联的非易失性存储器单元之间存储/读取任务数据。

109. 发明申请

US20130135918A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130135918A1
公开(公告)日：2013-05-30
申请号：US13420896
申请日：2012-03-15
申请人： Keiichi KUSHIDA
发明人： Keiichi KUSHIDA
IPC分类号： G11C11/22 , G11C11/40
CPC分类号： G11C13/004 , G11C8/16 , G11C13/0069 , G11C14/0072 , G11C14/0081 , G11C14/009 , G11C2013/0073
摘要： According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

110. 发明申请

US20110199810A1 Data Holding Device 有权
标题翻译：数据保持装置
公开(公告)号：US20110199810A1
公开(公告)日：2011-08-18
申请号：US13025395
申请日：2011-02-11
申请人： Hiromitsu Kimura , Jun Iida , Koji Nigoriike , Yoshinobu Ichida
发明人： Hiromitsu Kimura , Jun Iida , Koji Nigoriike , Yoshinobu Ichida
IPC分类号： G11C11/22
CPC分类号： G11C14/0072 , H03K3/356008 , H03K3/45 , H03K19/0016
摘要： A data holding device according to the present invention includes a loop structure portion LOOP for holding data using a plurality of logic gates (NAND3 and NAND4) connected in a loop, a nonvolatile storage portion (NVM) for storing in a nonvolatile manner the data held in the loop structure portion (LOOP) by using the hysteresis characteristics of ferroelectric elements, a circuit separating portion (SEP) for electrically separating the loop structure portion (LOOP) and the nonvolatile storage portion (NVM), and a set/reset controller (SRC) for generating a set signal (SNL) and reset signal (RNL) based on data stored in the nonvolatile storage portion (NVM), wherein the plurality of logic gates are each set and reset to an arbitrary output logic level in accordance with the set signal (SNL) and reset signal (RNL).
摘要翻译：根据本发明的数据保持装置包括用于使用以循环连接的多个逻辑门（NAND3和NAND4）保存数据的环路结构部分LOOP，用于以非易失性方式存储数据的非易失性存储部分（NVM）通过使用铁电元件的滞后特性在环路结构部分（LOOP）中，用于使环路结构部分（LOOP）和非易失性存储部分（NVM）电气分离的电路分离部分（SEP）和设置/复位控制器 SRC），用于根据存储在非易失性存储部分（NVM）中的数据产生设置信号（SNL）和复位信号（RNL），其中，多个逻辑门被设置并根据该信号被复位到任意的输出逻辑电平置位信号（SNL）和复位信号（RNL）。

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