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101. 发明授权

US06940500B2 Image display device and display driving method 有权
标题翻译：图像显示装置和显示驱动方法
公开(公告)号：US06940500B2
公开(公告)日：2005-09-06
申请号：US10252497
申请日：2002-09-23
申请人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
发明人： Hajime Washio , Yasuyoshi Kaise , Kazuhiro Maeda , Yasushi Kubota
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0248 , G09G2330/021
摘要： A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.
摘要翻译：扫描周期期间的数据信号线S的电位被充电到相应帧的数据信号的大致中间电位。因此，相对于数据信号线S的电位，每个像素电容器的电位不会发生极大的色散，从而可以限制流过每个像素的有源元件的漏电流的色散。因此，像素PIX的电位变化减小，使得可以在非扫描期间提高显示质量。也就是说，在有源矩阵型液晶显示器中，当通过在显示待机图像的同时将非扫描周期设置为比扫描周期充分大来降低帧频，从而实现低功耗，显示质量得到提高。

102. 发明授权

US06873313B2 Image display device and driving method thereof 有权
标题翻译：图像显示装置及其驱动方法
公开(公告)号：US06873313B2
公开(公告)日：2005-03-29
申请号：US09822768
申请日：2001-03-30
申请人： Hajime Washio , Nobuhiro Kuwabara , Hiroshi Yoneda , Shigeto Yoshida
发明人： Hajime Washio , Nobuhiro Kuwabara , Hiroshi Yoneda , Shigeto Yoshida
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3614 , G09G3/3685 , G09G2310/0232 , G09G2310/0251 , G09G2330/021
摘要： An image display device of this invention includes a pre-charging voltage stabilizing section having current controlling means and charge holding means which respectively include a resistor and a capacitor to stabilize a pre-charging voltage. The charge holding means holds a voltage to be supplied to data signal lines, and the current controlling means suppresses a current flow from a control signal generating circuit, thereby suppressing power fluctuation at the control signal generating circuit. This suppresses fluctuation in the pre-charging voltage and enables data signal lines to be charged to a predetermined voltage, thereby suppressing deterioration of image quality and an increase in power consumption of the image display device. Further, when using the pre-charging voltage stabilizing section and setting a portion of a display as a video data non-display area avoiding display of video data in a non-match image display mode to display at fixed brightness in the video data non-display area by a pre-charging voltage from a pre-charging circuit, a control signal is suspended in a fixed period, thus realizing a non-match image display mode to display a video image of an aspect ratio different from that of a screen of a display without impairing an image quality, and saving power.
摘要翻译：本发明的图像显示装置包括具有电流控制装置和电荷保持装置的预充电电压稳定部分，其分别包括用于稳定预充电电压的电阻器和电容器。电荷保持装置保持要提供给数据信号线的电压，并且电流控制装置抑制来自控制信号发生电路的电流，从而抑制控制信号发生电路的功率波动。这抑制了预充电电压的波动，并且能够使数据信号线被充电到预定电压，从而抑制图像质量的劣化和图像显示装置的功耗的增加。此外，当使用预充电电压稳定部分并且将显示器的一部分设置为视频数据非显示区域时，避免以不匹配的图像显示模式显示视频数据，以在视频数据非显示区域中以固定亮度显示，通过来自预充电电路的预充电电压来显示区域，控制信号以固定的时间段被暂停，从而实现不匹配的图像显示模式，以显示不同于屏幕的宽高比的视频图像显示而不损害图像质量，并且节省电力。

103. 发明申请

US20050057556A1 Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行
公开(公告)号：US20050057556A1
公开(公告)日：2005-03-17
申请号：US10949990
申请日：2004-09-23
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

104. 发明申请

US20050017065A1 Bidirectional shift register and display device incorporating same 失效
标题翻译：双向移位寄存器和包含其的显示装置
公开(公告)号：US20050017065A1
公开(公告)日：2005-01-27
申请号：US10860660
申请日：2004-06-04
申请人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
发明人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
IPC分类号： G11C19/00 , G06F5/01 , G06F17/00 , G09F9/00 , G09G3/00 , G09G3/20 , G09G3/36 , G11C8/04 , G11C19/28 , G11C19/34 , H03K23/44
CPC分类号： G06F5/01 , G09G3/006 , G09G3/20 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0289 , G09G2330/12
摘要： The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.
摘要翻译：本发明包括：移位寄存器部分，包括与时钟信号同步操作的多级触发器，用于根据外部提供的方向指示信号切换移位方向; 波形变化部分，用于改变处于第一预定阶段的触发器之一的信号输出的波形; 以及检查信号切换部，根据方向指示信号，切换波形变化部中波形变化的信号输出与第二个触发器中的一个触发器的信号输出之间的输出预定阶段。

105. 发明授权

US06724361B1 Shift register and image display device 有权
标题翻译：移位寄存器和图像显示设备
公开(公告)号：US06724361B1
公开(公告)日：2004-04-20
申请号：US09703918
申请日：2000-11-01
申请人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
发明人： Hajime Washio , Yasushi Kubota , Kazuhiro Maeda , Yasuyoshi Kaise , Michael James Brownlow , Graham Andrew Cairns
IPC分类号： G09G336
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2310/0289
摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.
摘要翻译：在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。产生具有与时钟信号的脉冲相同宽度的输出脉冲。

106. 发明授权

US06556162B2 Digital-to-analog converter and active matrix liquid crystal display 失效
标题翻译：数模转换器和有源矩阵液晶显示器
公开(公告)号：US06556162B2
公开(公告)日：2003-04-29
申请号：US09847661
申请日：2001-05-02
申请人： Michael James Brownlow , Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Hidehiko Yamashita , Yasushi Kubota , Hajime Washio
发明人： Michael James Brownlow , Graham Andrew Cairns , Catherine Rosinda Marie Armida Dachs , Hidehiko Yamashita , Yasushi Kubota , Hajime Washio
IPC分类号： H03M166
CPC分类号： H03M1/682 , G09G3/3688 , G09G2310/0248 , G09G2310/027 , H03M1/687 , H03M1/765 , H03M1/804
摘要： A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.
摘要翻译：数模转换器包括第一转换器级1，用于通过选择合适的低阻抗参考电压将k位输入信号的m个最高有效位转换为上限和下限电压极限VL和VH。第二转换器级2在由电压限制VL和VH限定的电压范围内执行k位输入的n个最低有效位的线性转换。包括开关SW1和SW2的预充电电路从负载CLOAD断开级2，负载CLOAD在预充电阶段期间被充电到电压极限VL。负载随后与电压限制VL断开并连接到级2的输出，以完成负载CLOAD到转换器输出电压的充电。

107. 发明授权

US06492972B1 Data signal line driving circuit and image display apparatus 有权
标题翻译：数据信号线驱动电路和图像显示装置
公开(公告)号：US06492972B1
公开(公告)日：2002-12-10
申请号：US09275261
申请日：1999-03-23
申请人： Yasushi Kubota , Tamotsu Sakai , Hajime Washio
发明人： Yasushi Kubota , Tamotsu Sakai , Hajime Washio
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G2300/0408 , G09G2320/0209
摘要： A data signal line driving circuit which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.
摘要翻译：数据信号线驱动电路，响应于多个采样信号顺次形成多个采样信号并连续采样输入信号以输出这些输入信号，其中采样信号分别表示彼此不同的采样周期，并且将每个采样信号的脉冲宽度规定为较小，使得每个采样信号的上升和下降彼此不重叠。

108. 发明授权

US06476637B1 Voltage level shifter and display device 有权
标题翻译：电压电平转换器和显示装置
公开(公告)号：US06476637B1
公开(公告)日：2002-11-05
申请号：US09568892
申请日：2000-05-11
申请人： Michael James Brownlow , Graham Andrew Cairns , Yasushi Kubota , Hajime Washio
发明人： Michael James Brownlow , Graham Andrew Cairns , Yasushi Kubota , Hajime Washio
IPC分类号： H03K190175
CPC分类号： H03K3/356113
摘要： A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.
摘要翻译：电压电平移位器包括交叉耦合源跟随器形式的输入级和放大器AMP形式的输出级，其可以具有单端或差分输入。源极跟随器包括晶体管M1和M2以及晶体管M3和M4。差分输入IN和！IN连接到晶体管M2和M4的栅极。从晶体管M3的漏极和晶体管M4的源极连接的节点B向晶体管M1的栅极提供偏置电压。类似地，偏置电压从晶体管M1的漏极和晶体管M2的源极连接到的节点A提供给晶体管M3的栅极。

109. 发明授权

US06262598B1 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US06262598B1
公开(公告)日：2001-07-17
申请号：US09517984
申请日：2000-03-03
申请人： Graham Andrew Cairns , Michael James Brownlow , Yasushi Kubota , Hajime Washio
发明人： Graham Andrew Cairns , Michael James Brownlow , Yasushi Kubota , Hajime Washio
IPC分类号： H03K190175
CPC分类号： G11C7/062 , H03K19/018521 , H03K19/018528 , H03K19/01855
摘要： A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.
摘要翻译：电压电平移位器包括连接在电源线vdd和反相输入端IN之间的互补晶体管T1，T2。晶体管T1的栅极连接到直接信号输入IN，而晶体管T2的栅极接收来自包括晶体管T3和T4的源极跟随器的直接输入信号的偏移版本。电平移位器还可以被实现为差分交叉耦合读出放大器，其中漏极负载晶体管的源极与差分输入交叉耦合。

110. 发明授权

US5610628A Driving device for a display panel and a driving method of the same 失效
公开(公告)号：US5610628A
公开(公告)日：1997-03-11
申请号：US447246
申请日：1995-05-22
申请人： Kunihiko Yamamoto , Kiyohisa Matsui , Yutaka Ishii , Norio Yasunishi , Toshihiro Nakamura , Hajime Washio , Koki Taniguchi
发明人： Kunihiko Yamamoto , Kiyohisa Matsui , Yutaka Ishii , Norio Yasunishi , Toshihiro Nakamura , Hajime Washio , Koki Taniguchi
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3625
摘要： A driving device for a display apparatus having excellent contrast and a high display quality without crosstalk and display irregularities, and a driving method for the same are provided. In the driving device, scanning signals and data signals having a plurality of periodical inactive portions in one frame are applied to respective display dots. In the inactive term, a fixed voltage is applied to each of the display dots. The signal applied to the display dot is divided into small terms by the inactive portions, resulting in more high frequency components in a voltage signal applied to the display dot. As a result, the frequency components of a driving signal applied to the display dot are averaged. Further, a complete orthogonal function having 2.sup.r base function series is used, and a desired display data is completely reproduced on the display apparatus by an arithmetic process assuming auxiliary data in accordance with the number of the scanning electrodes.

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