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101. 发明申请

US20120187491A1 METHOD FOR FORMING RETROGRADED WELL FOR MOSFET 有权
标题翻译：用于形成MOSFET的退火方法
公开(公告)号：US20120187491A1
公开(公告)日：2012-07-26
申请号：US13429948
申请日：2012-03-26
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/772
CPC分类号： H01L21/187 , H01L21/6835 , H01L21/84 , H01L27/12 , H01L29/1083 , H01L2221/6835 , H01L2221/68368
摘要： A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.
摘要翻译：提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。形成接触至少一个半导体器件和第一半导体层的处理结构。去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含的回归井掺杂剂。退火井可以进行激光退火。

102. 发明申请

US20120168881A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120168881A1
公开(公告)日：2012-07-05
申请号：US13142591
申请日：2011-01-27
申请人： Haizhou Yin , Huicai Zhong , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huicai Zhong , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/7846 , H01L21/76224 , H01L29/045 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.
摘要翻译：本发明提供一种半导体器件及其制造方法。制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。

103. 发明申请

US20120146103A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146103A1
公开(公告)日：2012-06-14
申请号：US13378206
申请日：2011-02-27
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/165 , H01L21/30608 , H01L29/1054 , H01L29/1083 , H01L29/517 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/6659 , H01L29/66651 , H01L29/7834 , H01L29/7849
摘要： The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.
摘要翻译：本申请公开了半导体器件及其制造方法。其中，所述半导体器件包括：半导体衬底; 嵌入在半导体衬底中的应力器; 设置在所述应力器上的通道区域; 设置在通道区域上的栅极堆叠; 源极/漏极区域，设置在沟道区域的两侧并且嵌入在半导体衬底中; 其中，所述应力器的表面包括顶壁，底壁和侧壁，所述侧壁包括第一侧壁和第二侧壁，所述第一侧壁连接所述顶壁和所述第二侧壁，所述第二侧连接第一侧壁和底壁的壁，第一侧壁和第二侧壁之间的角度小于180°，第一侧壁和第二侧壁相对于平行于半导体的平面大致对称基质。本发明的实施例可应用于半导体器件制造中的应力工程技术。

104. 发明申请

US20120112252A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120112252A1
公开(公告)日：2012-05-10
申请号：US13380380
申请日：2011-02-27
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, which lies in covering a first dielectric layer with a second dielectric layer, forming a first contact hole with a small inner diameter within the second dielectric layer first, then etching the first dielectric layer to form a second contact hole with a much great inner diameter, and finally filling a conductive material into the first contact hole and the second contact hole to form contact plugs. Accordingly, the present invention further provides a semiconductor structure favorable for reducing contact resistance.
摘要翻译：本发明提供了一种制造半导体结构的方法，该半导体结构覆盖第一介电层与第二介电层，首先在第二电介质层内形成具有小内径的第一接触孔，然后蚀刻第一介电层至形成具有非常大的内径的第二接触孔，最后将导电材料填充到第一接触孔和第二接触孔中以形成接触塞。因此，本发明还提供有利于降低接触电阻的半导体结构。

105. 发明授权

US08138029B2 Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) 失效
标题翻译：具有半导体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的不对称结或反向晕轮廓的结构和方法
公开(公告)号：US08138029B2
公开(公告)日：2012-03-20
申请号：US12686402
申请日：2010-01-13
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L21/00
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

106. 发明申请

US20120061735A1 SEMICONDUCTOR DEVICE WITH STRESS TRENCH ISOLATION AND METHOD FOR FORMING THE SAME 有权
标题翻译：具有应力裂解隔离的半导体器件及其形成方法
公开(公告)号：US20120061735A1
公开(公告)日：2012-03-15
申请号：US13257725
申请日：2011-01-27
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823412 , H01L21/823807 , H01L21/823878
摘要： A semiconductor device with stress trench isolation and a method for forming the same are provided. The method includes: providing a silicon substrate; forming first trenches and second trenches on the silicon substrate, wherein an extension direction of the first trenches is perpendicular to that of the second trenches; forming a first dielectric layer in the first trenches and forming a second dielectric layer in the second trenches; and forming a gate stack on a portion of the silicon substrate surrounded by the first trenches and the second trenches, wherein a channel length direction under the gate stack is parallel to the extension direction of the first trenches, indices of crystal plane of the silicon substrate are {100}, and the extension direction of the first trenches is along the crystal orientation . The embodiments of the present invention can improve response speed and performance of the devices.
摘要翻译：提供了一种具有应力沟槽隔离的半导体器件及其形成方法。该方法包括：提供硅衬底; 在所述硅衬底上形成第一沟槽和第二沟槽，其中所述第一沟槽的延伸方向垂直于所述第二沟槽的延伸方向; 在所述第一沟槽中形成第一电介质层，并在所述第二沟槽中形成第二电介质层; 以及在由所述第一沟槽和所述第二沟槽围绕的所述硅衬底的一部分上形成栅极堆叠，其中所述栅叠层下方的沟道长度方向平行于所述第一沟槽的延伸方向，所述硅衬底的晶面的折射率是{100}，并且第一沟槽的延伸方向是沿着晶体取向<110>。本发明的实施例可以提高设备的响应速度和性能。

107. 发明申请

US20120049249A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120049249A1
公开(公告)日：2012-03-01
申请号：US13062733
申请日：2010-09-20
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7834 , H01L21/76224 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.
摘要翻译：半导体结构及其制造方法。半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件，每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物，其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。

108. 发明申请

US20120025319A1 STRUCTURE AND METHOD FOR MAKING METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) WITH ISOLATION LAST PROCESS 失效
标题翻译：用于制造具有隔离最近工艺的金属半导体场效应晶体管（MOSFET）的结构和方法
公开(公告)号：US20120025319A1
公开(公告)日：2012-02-02
申请号：US12844478
申请日：2010-07-27
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/84 , H01L21/76224 , H01L21/76898 , H01L21/823481 , H01L27/1203
摘要： In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the substrate from a second surface of the substrate that is opposite the first surface of the substrate, wherein the trench terminates on the placeholder dielectric. The trench is filled with a dielectric material.
摘要翻译：在一个实施例中，提供了提供半导体器件的方法，其中代替在形成半导体器件之前形成隔离区域，在半导体器件之后形成隔离区域。在一个实施例中，该方法包括在半导体衬底上形成半导体器件。在与半导体器件相邻的衬底的第一表面的一部分上形成占位电介质。沟槽从衬底的与衬底的第一表面相对的第二表面蚀刻到衬底中，其中沟槽终止在占位符电介质上。沟槽填充有电介质材料。

109. 发明申请

US20120001198A1 ISOLATION REGION, SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME 有权
标题翻译：分离区，半导体器件及其形成方法
公开(公告)号：US20120001198A1
公开(公告)日：2012-01-05
申请号：US13119129
申请日：2011-02-18
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/16 , H01L21/336 , H01L21/31 , H01L29/06 , H01L29/772
CPC分类号： H01L21/3083 , H01L21/76232 , H01L29/66636 , H01L29/78
摘要： An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided. In the semiconductor device, a material of the semiconductor substrate is interposed between a second groove bearing a semiconductor layer for forming an S/D region and the first and second sidewalls. The present invention is beneficial to reduce leakage current.
摘要翻译：提供隔离区域。隔离区域包括第一凹槽和填充第一凹槽的绝缘层。第一凹槽被嵌入到半导体衬底中，并且包括从底表面延伸并连接到第一侧壁的第一侧壁，底表面和第二侧壁。半导体衬底的第一侧壁和法线之间的角度大于标准值。还提供了形成隔离区域的方法。该方法包括：在半导体衬底上形成第一沟槽，其中第一沟槽的侧壁和半导体衬底的法线之间的角度大于标准值; 在所述侧壁上形成掩模以通过使用所述掩模在所述半导体衬底上形成第二沟槽; 以及形成绝缘层以填充所述第一和第二沟槽。还提供一种半导体器件及其形成方法。在半导体器件中，半导体衬底的材料插入在用于形成S / D区域的半导体层的第二沟槽和第一和第二侧壁之间。本发明有益于减少漏电流。

110. 发明申请

US20110316088A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US20110316088A1
公开(公告)日：2011-12-29
申请号：US13201827
申请日：2011-02-24
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A semiconductor structure and a method for forming the same are provided. The structure comprises a semiconductor substrate (100) with an nMOSFET region (102) and a pMOSFET region (104) on it. An nMOSFET structure and a pMOSFET structure are formed in the nMOSFET region (102) and the pMOSFET region (104), respectively. The nMOSFET structure comprises a first channel region (182) formed in the nMOSFET region (102) and a first gate stack formed in the first channel region (182). The nMOSFET structure is covered with a compressive-stressed material layer (130) to apply a tensile stress to the first channel region (182). The pMOSFET structure comprises a second channel region (184) formed in the pMOSFET region (104) and a second gate stack formed in the second channel region (184). The pMOSFET structure is covered with a tensile-stressed material layer (140) to apply a compressive stress to the second channel region (184).
摘要翻译：提供半导体结构及其形成方法。该结构包括其上具有nMOSFET区域（102）和pMOSFET区域（104）的半导体衬底（100）。 nMOSFET结构和pMOSFET结构分别形成在nMOSFET区域（102）和pMOSFET区域（104）中。 nMOSFET结构包括形成在nMOSFET区域（102）中的第一沟道区（182）和形成在第一沟道区（182）中的第一栅叠层。 nMOSFET结构用压应力材料层（130）覆盖，以向第一沟道区域（182）施加拉伸应力。 pMOSFET结构包括形成在pMOSFET区域（104）中的第二沟道区（184）和形成在第二沟道区（184）中的第二栅叠层。 pMOSFET结构被拉伸应力材料层（140）覆盖，以向第二通道区域（184）施加压缩应力。

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