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101. 发明授权

US06529426B1 Circuit and method for varying a period of an internal control signal during a test mode 失效
标题翻译：在测试模式期间改变内部控制信号的周期的电路和方法
公开(公告)号：US06529426B1
公开(公告)日：2003-03-04
申请号：US08816943
申请日：1997-01-28
申请人： Todd A. Merritt , Paul S. Zagar
发明人： Todd A. Merritt , Paul S. Zagar
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C11/401 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C2029/5004
摘要： The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a period of an internal control signal to stress the DRAM during a test mode.
摘要翻译：本发明是具有在板上制造的电子测试键的动态随机存取存储器（DRAM）器件，并且是用于测试DRAM的方法。电子测试键产生在测试模式期间影响内部控制信号的周期的变化以胁迫DRAM的信号。

102. 发明授权

US06504743B2 Die architecture accommodating high-speed semiconductor devices 有权
公开(公告)号：US06504743B2
公开(公告)日：2003-01-07
申请号：US10007571
申请日：2001-11-07
申请人： Donald M. Morgan , Todd A. Merritt
发明人： Donald M. Morgan , Todd A. Merritt
IPC分类号： G11C502
CPC分类号： G11C5/025 , H01L27/10897 , H01L2224/49171
摘要： In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame “fingers” for use with wide data busses as part of high speed, multiple band memory integrated circuits.

103. 发明授权

US06484278B1 Method and apparatus for testing an embedded DRAM 有权
标题翻译：用于测试嵌入式DRAM的方法和装置
公开(公告)号：US06484278B1
公开(公告)日：2002-11-19
申请号：US09573074
申请日：2000-05-16
申请人： Todd A. Merritt , Donald M. Morgan , Huy Thanh Vo
发明人： Todd A. Merritt , Donald M. Morgan , Huy Thanh Vo
IPC分类号： G11C2900
CPC分类号： G11C29/14
摘要： A test circuit tests for defective memory cells in a memory portion of an Embedded DRAM. The Embedded DRAM includes an array of memory cells. The test circuit includes a test mode terminal adapted to receive a test mode signal and a plurality of comparison circuits. Each comparison circuit includes a first input adapted to receive a read data signal and a second input adapted to receive an expect data signal. Each comparison circuit compares the binary values of the read and expect data signals and develops and inactive error signal on an output when the compared signals have the same binary values, and develops an active error signal when the compared signals have different binary values. A storage circuit is coupled to the outputs of the comparison circuits. The storage circuit latches the error signals output by the comparison circuits and sequentially transfers the latched error signals onto a data terminal of the Embedded DRAM. A test control circuit is coupled to the comparison circuits, the test mode termninal, and the storage circuit. The test control circuit operates when the test mode signal is active, to apply data from addressed memory cells respectively on the first inputs of the comparison circuits. The test control circuit also applies respective expect data on the second inputs of the comparison circuits and controls the storage circuit to latch the resulting error signals and thereafter sequentially transfer the latched error signals onto the data terminal. The test circuit may include additional stages of comparison circuits to further compress read test data, as well as additional storage circuits for storing such additional compressed data.
摘要翻译：测试电路测试嵌入式DRAM的存储器部分中的有缺陷的存储单元。嵌入式DRAM包括一组存储单元。测试电路包括适于接收测试模式信号的测试模式终端和多个比较电路。每个比较电路包括适于接收读取数据信号的第一输入和适于接收期望数据信号的第二输入。每个比较电路比较读取和期望数据信号的二进制值，并且当比较的信号具有相同的二进制值时，在输出上产生和无效的误差信号，并且当比较的信号具有不同的二进制值时产生有效的误差信号。存储电路耦合到比较电路的输出端。存储电路锁存由比较电路输出的误差信号，并将锁存的误差信号依次传送到嵌入式DRAM的数据端。测试控制电路耦合到比较电路，测试模式termninal和存储电路。当测试模式信号有效时，测试控制电路工作，分别将来自寻址的存储器单元的数据应用于比较电路的第一输入端。测试控制电路还对比较电路的第二输入端施加各自的期望数据，并且控制存储电路以锁存所得到的误差信号，然后将锁存的误差信号顺序地传送到数据终端。测试电路可以包括用于进一步压缩读取测试数据的另外的比较电路级，以及用于存储这种附加压缩数据的附加存储电路。

104. 发明授权

US06363032B1 Programmable counter circuit for generating a sequential/interleave address sequence 有权
公开(公告)号：US06363032B1
公开(公告)日：2002-03-26
申请号：US09773676
申请日：2001-02-02
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C800
摘要： A programmable counter circuit for use in semiconductor memories for generating both sequential and interleave address sequences for block data accesses is disclosed. The output and complementary output of the counter for a previous bit are multiplexed to send the proper carry bit information to the counter for the next bit. In interleave mode, the carry bit forces the row/column counter to count in an interleave address sequence. In sequential mode, the start address of the memory access is captured and held. Either the output or complementary output of the counter for a previous bit is used to control the counter of the next bit based on the captured start address bit. The counter can be programmed to automatically increment the memory address in both a binary and interleave sequence in order to increase the access speed for blocks of sequential data in semiconductor memories.

105. 发明授权

US06320779B1 Die architecture accommodating high-speed semiconductor devices 有权
标题翻译：适合高速半导体器件的模块架构
公开(公告)号：US06320779B1
公开(公告)日：2001-11-20
申请号：US09652839
申请日：2000-08-31
申请人： Donald M. Morgan , Todd A. Merritt
发明人： Donald M. Morgan , Todd A. Merritt
IPC分类号： G11C502
CPC分类号： G11C5/025 , H01L27/10897 , H01L2224/49171
摘要： In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame “fingers” for use with wide data busses as part of high speed, multiple band memory integrated circuits.
摘要翻译：在半导体存储器件中，提供了将存储器阵列布置成长而窄的结构的管芯结构。然后可以沿着相应形状的模具的长边放置焊盘。因此，该架构与用于宽数据总线的短引线框“手指”兼容，作为高速，多频带存储器集成电路的一部分。

106. 发明授权

US06285243B1 High-voltage charge pump circuit 有权
标题翻译：高压电荷泵电路
公开(公告)号：US06285243B1
公开(公告)日：2001-09-04
申请号：US09511577
申请日：2000-02-23
申请人： Richard A. Mecier , Todd A. Merritt
发明人： Richard A. Mecier , Todd A. Merritt
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： Charge pump circuits are described that transfer a voltage signal in an output stage without signal-level degradation. Where a voltage signal may cause damage to circuitry or semiconductor breakdown, at least one bypass technique is engaged to inhibit such damage or breakdown.
摘要翻译：描述了在输出级中传送电压信号而没有信号电平降级的电荷泵电路。如果电压信号可能导致电路损坏或半导体击穿，则至少采用一种旁路技术来抑制这种损坏或故障。

107. 发明授权

US06192002B1 Memory device with command buffer 有权
标题翻译：具有写入脉冲串的存储器件
公开(公告)号：US06192002B1
公开(公告)日：2001-02-20
申请号：US09143173
申请日：1998-08-28
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1072
摘要： A memory device includes a memory array, an external clock terminal, and control logic. The memory array is arranged in rows and columns. The external clock terminal is adapted to receive an external clock signal. The external clock signal has at least a first cycle and a second cycle. The first cycle includes a first edge and the second cycle includes a second edge. The control logic is coupled to the memory array and the external clock terminal and adapted to write to a first plurality of the columns in a specified row during the first and second cycles. The control logic is further adapted to suspend the external clock signal to suppress the second edge of the second cycle while writing to the first plurality of the columns. A method for accessing a memory device arranged in rows and columns is provided. The method includes receiving an external clock signal. The external clock signal has at least a first cycle and a second cycle. The first cycle includes a first edge and the second cycle includes a second edge. A first plurality of columns in a specified row are written to during the first and second cycles. The external clock signal is suspended to suppress the second edge of the second cycle while writing to the first plurality of the columns.
摘要翻译：存储器件包括存储器阵列，外部时钟端子和控制逻辑。存储器阵列以行和列排列。外部时钟端子适于接收外部时钟信号。外部时钟信号至少具有第一周期和第二周期。第一周期包括第一边缘，第二周期包括第二边缘。控制逻辑耦合到存储器阵列和外部时钟端子，并且适于在第一和第二周期期间写入指定行中的第一多个列。控制逻辑还适于在写入第一多个列时暂停外部时钟信号以抑制第二周期的第二边缘。提供了一种用于访问以行和列排列的存储器件的方法。该方法包括接收外部时钟信号。外部时钟信号至少具有第一周期和第二周期。第一周期包括第一边缘，第二周期包括第二边缘。在第一和第二周期期间，将指定行中的第一多个列写入。外部时钟信号被暂停以在写入第一多个列时抑制第二周期的第二边缘。

108. 发明授权

US06190972B1 Method for storing information in a semiconductor device 失效
标题翻译：用于在半导体器件中存储信息的结构和方法
公开(公告)号：US06190972B1
公开(公告)日：2001-02-20
申请号：US08946027
申请日：1997-10-07
申请人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
发明人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
IPC分类号： H01L218246
CPC分类号： G01R31/3181 , G11C17/10 , H01L27/112
摘要： A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer. Each of the storage elements is formed in a predetermined state such that they collectively store a digital value that identifies a mask used to form the conductive layer.
摘要翻译：半导体器件包括形成在衬底上的多个导电层。共同组成存储元件的只读存储元件（例如熔丝元件）的两个电互相耦合部分分别形成在不同的一个导电层中。存储元件具有存储状态，并且每个部分具有导电性。可以通过改变其中一个部分的电导率来改变存储元件的存储状态。另外，多个存储元件可以并联耦合以形成存储模块。存储模块的每个存储元件可以包括各自形成在不同导电层中的多个存储部分。存储元件可以存储用于形成半导体器件的掩模集的版本号。或者，在衬底上形成导电层，并且在导电层中形成一个或多个只读存储元件。每个存储元件形成为预定状态，使得它们共同地存储识别用于形成导电层的掩模的数字值。

109. 发明授权

US6154864A Read only memory embedded in a dynamic random access memory 失效
标题翻译：只读存储器嵌入在动态随机存取存储器中
公开(公告)号：US6154864A
公开(公告)日：2000-11-28
申请号：US81133
申请日：1998-05-19
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/10 , G11C7/20 , G11C11/00 , G06F11/00
CPC分类号： G11C7/10 , G11C11/005 , G11C7/20
摘要： The present invention is embodied in a method and apparatus which provides a ROM embedded in an DRAM utilizing unused portions of the DRAM. By hardwiring the unused digitlines of the DRAM to either a specified voltage or ground, the outputs of the sense amplifiers associated with those unused digitlines can be programmed to output a specific logic state. By combining the outputs from several sense amplifiers, a fixed bit pattern can be produced. The fixed bit pattern can be used, for example, to generate a test data pattern for a Built-in Self Test or to generate an initialization sequence.
摘要翻译：本发明体现在一种使用DRAM的未使用部分来提供嵌入在DRAM中的ROM的方法和装置。通过将DRAM的未使用的数字线硬接线到指定的电压或接地，与那些未使用的数字线相关联的读出放大器的输出可被编程为输出特定的逻辑状态。通过组合来自多个读出放大器的输出，可以产生固定的位模式。固定位模式可用于例如生成用于内置自检的测试数据模式或生成初始化序列。

110. 发明授权

US6118711A Apparatus for testing redundant elements in a packaged semiconductor memory device 有权
公开(公告)号：US6118711A
公开(公告)日：2000-09-12
申请号：US227483
申请日：1999-01-07
申请人： Todd A. Merritt
发明人： Todd A. Merritt
IPC分类号： G11C7/00 , G11C29/24
CPC分类号： G11C29/24
摘要： During compression mode testing of a semiconductor memory device, a memory address is compressed to free up 2 or more bits in the address (e.g., an 11-bit address is compressed to 9-bits, freeing up 2 bits). Redundant element enable circuitry is coupled to one or more pins on a packaged chip that are unused during the compression mode testing. The circuitry receives control signals from external testing circuitry to select between the primary memory array in the chip, and redundant rows and columns of memory in the chip. As a result, during compressed address mode testing of the chip, a full 11-bit word is input to test the circuitry, but where 2 of the 11 bits allow the external circuitry to toggle between, and thereby selectively access, the rows and columns of primary and redundant memory in the chip. Alternatively, the circuitry can also be coupled to a non-connected pin on the packaged chip so as to operate during a non-compression mode testing.

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