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101. 发明申请

US20070057292A1 SONOS type non-volatile semiconductor devices and methods of forming the same 审中-公开
标题翻译： SONOS型非易失性半导体器件及其形成方法
公开(公告)号：US20070057292A1
公开(公告)日：2007-03-15
申请号：US11518656
申请日：2006-09-11
申请人： Hong-Bae Park , Yu-Gyun Shin
发明人： Hong-Bae Park , Yu-Gyun Shin
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L29/40117
摘要： A SONOS type non-volatile semiconductor device includes a semiconductor substrate, source/drain regions doped with impurities formed in the semiconductor substrate, a channel region formed in the semiconductor substrate between the source/drain regions, a tunnel insulation layer formed on the channel region, a charge-trapping layer formed on the tunnel insulation layer, a blocking insulation layer formed on the charge-trapping layer, and a gate electrode formed on the blocking insulation layer. The charge-trapping layer includes aluminum nitride having a chemical formula AlxNy and/or the blocking insulation layer includes aluminum nitride having a chemical formula AlpNq, such that x, y, p, and q are positive integers, x and y satisfy a relation x>y, and p and q satisfy a relation p
摘要翻译： SONOS型非易失性半导体器件包括半导体衬底，掺杂在半导体衬底中形成的杂质的源/漏区，形成在源/漏区之间的半导体衬底中的沟道区，形成在沟道区上的隧道绝缘层形成在隧道绝缘层上的电荷俘获层，形成在电荷俘获层上的阻挡绝缘层，以及形成在阻挡绝缘层上的栅电极。电荷捕获层包括具有化学式Al x N y Y的氮化铝和/或阻挡绝缘层包括具有化学式为Al < x，y，p和q是正整数，x和y满足关系x> y，p和q满足关系p

102. 发明申请

US20070026621A1 Non-volatile semiconductor devices and methods of manufacturing the same 审中-公开
标题翻译：非易失性半导体器件及其制造方法
公开(公告)号：US20070026621A1
公开(公告)日：2007-02-01
申请号：US11542808
申请日：2006-10-04
申请人： Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang , Taek-Soo Jeon , Hye-Lan Lee
发明人： Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang , Taek-Soo Jeon , Hye-Lan Lee
IPC分类号： H01L21/331
CPC分类号： H01L29/792 , H01L27/10817 , H01L27/10852 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/513
摘要： Provided herein is a non-volatile semiconductor device that includes a tunnel insulation layer pattern formed on a semiconductor substrate, a charge trapping layer pattern formed on the tunnel insulation layer pattern, a blocking dielectric layer pattern formed on the charge trapping layer pattern and a tantalum carbon nitride layer pattern formed on the blocking dielectric layer pattern. The tantalum carbon nitride layer pattern may be formed by a CVD process using a source gas including a tantalum metal complex, wherein one or more of ligands of the tantalum metal complex include nitrogen and carbon. Since the non-volatile semiconductor device includes the tantalum carbon nitride layer pattern as an electrode, the non-volatile semiconductor device according to embodiments of the invention may have improved response speed and require relatively low driving voltage.
摘要翻译：本文提供了一种非易失性半导体器件，其包括形成在半导体衬底上的隧道绝缘层图案，形成在隧道绝缘层图案上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡介电层图案和钽形成在阻挡电介质层图案上的碳氮化物层图案。钽碳氮化物层图案可以通过使用包括钽金属络合物的源气体的CVD工艺形成，其中一个或多个钽金属络合物的配体包括氮和碳。由于非易失性半导体器件包括作为电极的碳氮化钽层图案，根据本发明的实施例的非易失性半导体器件可以具有改善的响应速度并且需要相对较低的驱动电压。

103. 发明申请

US20060151826A1 Semiconductor device having a barrier layer and method of manufacturing the same 审中-公开
标题翻译：具有阻挡层的半导体器件及其制造方法
公开(公告)号：US20060151826A1
公开(公告)日：2006-07-13
申请号：US11326286
申请日：2006-01-06
申请人： Beom-Jun Jin , Hong-Bae Park , Seong-Geon Park , Yu-Gyun Shin , Sang-Bom Kang
发明人： Beom-Jun Jin , Hong-Bae Park , Seong-Geon Park , Yu-Gyun Shin , Sang-Bom Kang
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/823425 , H01L21/823437 , H01L27/11568
摘要： A semiconductor device may include a gate structure having a gate insulation layer formed on a substrate, and a gate electrode formed on the gate insulation layer. A composite barrier layer may be formed on the gate structure.
摘要翻译：半导体器件可以包括具有形成在衬底上的栅极绝缘层的栅极结构和形成在栅极绝缘层上的栅电极。可以在栅极结构上形成复合阻挡层。

104. 发明申请

US20060145254A1 Semiconductor devices including carrier accumulation layers and methods for fabricating the same 失效
标题翻译：包括载体积聚层的半导体器件及其制造方法
公开(公告)号：US20060145254A1
公开(公告)日：2006-07-06
申请号：US11322335
申请日：2005-12-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/28247 , H01L21/28273 , H01L21/28282 , H01L29/6659 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.
摘要翻译：半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。表面绝缘层与源极/漏极区之间的界面包括多个界面状态。紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。载体积聚层沿着间隔物下的界面延伸。还讨论了相关方法。

105. 发明授权

US08691649B2 Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices 有权
标题翻译：形成凹槽阵列晶体管的方法和制造半导体器件的方法
公开(公告)号：US08691649B2
公开(公告)日：2014-04-08
申请号：US13151494
申请日：2011-06-02
申请人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要翻译：在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。可以在栅极氧化物层上形成栅电极以填充凹部。源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。因此，氧化物层可以具有均匀的厚度分布和致密结构。

106. 发明申请

US20110180879A1 CMOS TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND SEMICONDUCTOR MODULE INCLUDING THE DEVICE 有权
标题翻译： CMOS晶体管，包括晶体管的半导体器件和包括器件的半导体器件
公开(公告)号：US20110180879A1
公开(公告)日：2011-07-28
申请号：US12972961
申请日：2010-12-20
申请人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hye-Lan Lee , Hong-Bae Park , Sang-Jin Hyun , Yu-Gyun Shin , Sug-Hun Hong , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L23/522 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823842 , H01L21/82385 , H01L21/823871 , H01L23/485 , H01L27/0629 , H01L27/0805 , H01L27/0811 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.
摘要翻译：提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。半导体衬底的第一和第二区域可以具有不同的导电类型。第一和第二互连结构可以设置在半导体衬底上。第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。半导体器件可以设置在半导体模块中。

107. 发明申请

US20100197089A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH METAL-SEMICONDUCTOR COMPOUND SOURCE/DRAIN CONTACT REGIONS 审中-公开
标题翻译：用金属半导体复合源/漏极接触区制造半导体器件的方法
公开(公告)号：US20100197089A1
公开(公告)日：2010-08-05
申请号：US12699491
申请日：2010-02-03
申请人： Jin-Bum Kim , Yu-Gyun Shin , Jung-Yun Won , In-Sun Jung , Jun-Ho Lee
发明人： Jin-Bum Kim , Yu-Gyun Shin , Jung-Yun Won , In-Sun Jung , Jun-Ho Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/28518 , H01L21/28525 , H01L21/2855 , H01L21/32053 , H01L21/76814 , H01L21/76838 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L21/823871 , H01L23/53238 , H01L23/53266 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer.
摘要翻译：制造半导体器件的方法包括在半导体衬底上和/或半导体衬底中形成晶体管，其中晶体管包括源极/漏极区域和设置在与源极/漏极区域相邻的沟道区域上的栅极图案。在晶体管上形成绝缘层并图案化以暴露源/漏区域。在暴露的源极/漏极区域和绝缘层的相邻部分上形成半导体源极层。在半导体源层上形成金属源层。进行退火以在源极/漏极区域上形成第一金属 - 半导体化合物区域和在绝缘层的相邻部分上形成第二金属 - 半导体化合物区域。第一金属 - 半导体化合物区域可以比第二金属 - 半导体化合物区域厚。金属源层可以包括金属层和金属氮化物阻挡层。

108. 发明授权

US07419918B2 Methods of forming a thin-film structure, methods of manufacturing non-volatile semiconductor devices using the same, and resulting non-volatile semiconductor devices 有权
标题翻译：形成薄膜结构的方法，制造使用其的非易失性半导体器件的制造方法以及所得的非易失性半导体器件
公开(公告)号：US07419918B2
公开(公告)日：2008-09-02
申请号：US11399670
申请日：2006-04-06
申请人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Ji-Hyun Kim , Young-Jin Noh
发明人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Ji-Hyun Kim , Young-Jin Noh
IPC分类号： H01L21/31
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： In a method of forming a thin-film structure employed in a non-volatile semiconductor device, an oxide film is formed on a substrate. An upper nitride film is formed on the oxide film by nitrifying an upper portion of the oxide film through a plasma nitration process. A lower nitride film is formed between the substrate and the oxide film by nitrifying a lower portion of the oxide film through a thermal nitration process. A damage to the thin-film structure generated in the plasma nitration process may be at least partially cured in the thermal nitration process, and/or may be cured in a post-thermal treatment process.
摘要翻译：在非易失性半导体器件中使用的薄膜结构的形成方法中，在基板上形成氧化膜。通过等离子体硝化工艺对氧化膜的上部进行硝化，在氧化物膜上形成上部氮化物膜。通过热硝化处理使氧化膜的下部硝化，在基板和氧化膜之间形成下部氮化膜。在等离子体硝化过程中产生的薄膜结构的损坏可以在热硝化过程中至少部分地固化，和/或可以在后热处理过程中固化。

109. 发明申请

US20070166931A1 Methods of Manufacturing A Semiconductor Device for Improving the Electrical Characteristics of A Dielectric Film 审中-公开
标题翻译：制造用于改善介质膜的电气特性的半导体器件的方法
公开(公告)号：US20070166931A1
公开(公告)日：2007-07-19
申请号：US11567971
申请日：2006-12-07
申请人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
发明人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28185 , H01L21/3105 , H01L29/513 , H01L29/517
摘要： A method of manufacturing a semiconductor device includes depositing a high-dielectric film on a semiconductor substrate and performing an oxygen plasma treatment on the high-dielectric film deposited on the semiconductor substrate. The method further includes forming an electrode on the oxygen-plasma treated high-dielectric film.
摘要翻译：制造半导体器件的方法包括在半导体衬底上沉积高电介质膜并对沉积在半导体衬底上的高电介质膜进行氧等离子体处理。该方法还包括在氧等离子体处理的高电介质膜上形成电极。

110. 发明申请

US20070134415A1 Oxidation Treatment Apparatus and Method 审中-公开
标题翻译：氧化处理装置及方法
公开(公告)号：US20070134415A1
公开(公告)日：2007-06-14
申请号：US11563980
申请日：2006-11-28
申请人： Ki-Hyun Hwang , U-In Chung , Yu-Gyun Shin , Jae-Young Ahn , Jin-Gyun Kim
发明人： Ki-Hyun Hwang , U-In Chung , Yu-Gyun Shin , Jae-Young Ahn , Jin-Gyun Kim
IPC分类号： C23C16/00 , B05D3/04 , B05D7/00 , B05D1/02
CPC分类号： H01L21/02233 , H01L21/31654
摘要： An oxidation treatment apparatus for oxidizing a surface of a substrate includes a process chamber for performing a process, a boat supporting the substrate and disposed in the process chamber during the process and a first ozone supply unit supplying ozone to the process chamber. The first ozone supply unit includes an ozone generator disposed at an exterior of the process chamber and an ozone spray nozzle disposed in the process chamber to spray the ozone supplied from the ozone generator into the process chamber.
摘要翻译：用于氧化基板表面的氧化处理装置包括处理过程的处理室，支撑基板的船，并且在处理过程中设置在处理室中，以及向处理室供应臭氧的第一臭氧供给单元。第一臭氧供应单元包括设置在处理室外部的臭氧发生器和设置在处理室中的臭氧喷嘴，以将从臭氧发生器供应的臭氧喷射到处理室中。

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