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101. 发明授权

US06687838B2 Low-power processor hint, such as from a PAUSE instruction 有权
标题翻译：低功耗处理器提示，例如从PAUSE指令
公开(公告)号：US06687838B2
公开(公告)日：2004-02-03
申请号：US09733821
申请日：2000-12-07
申请人： Doron Orenstien , Ronny Ronen
发明人： Doron Orenstien , Ronny Ronen
IPC分类号： G06F132
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , G06F9/30083 , G06F9/3009 , G06F9/30189 , G06F9/3836 , G06F9/3851 , Y02D10/126 , Y02D10/172
摘要： A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.
摘要翻译：系统和相应的方法使用“处理器慢速模式”在单个线程或多线程环境中使用PAUSE指令作为低功耗提示。一个实施例实际上降低了处理器时钟的频率。另外一个实施例通过在N个时钟周期内门控M个时钟周期来实际上降低处理器时钟的频率。当所有线程发出PAUSE指令时，处理器进入慢速模式并保持一段时间。此后，处理器返回正常模式。或者，诸如中断或异常的事件可以使处理器从慢速模式返回正常模式。

102. 发明授权

US06631445B2 Cache structure for storing variable length data 有权
公开(公告)号：US06631445B2
公开(公告)日：2003-10-07
申请号：US10372194
申请日：2003-02-25
申请人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
发明人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
IPC分类号： G06F1200
CPC分类号： G06F12/0846 , G06F12/0875 , G06F12/0886
摘要： A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.

103. 发明授权

US06601161B2 Method and system for branch target prediction using path information 有权
标题翻译：使用路径信息进行分支目标预测的方法和系统
公开(公告)号：US06601161B2
公开(公告)日：2003-07-29
申请号：US09223303
申请日：1998-12-30
申请人： Lihu Rappoport , Ronny Ronen , Nicolas Kacevas , Oded Lempel
发明人： Lihu Rappoport , Ronny Ronen , Nicolas Kacevas , Oded Lempel
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.
摘要翻译：一种用于预测微处理器当前指令的分支目标的系统和方法，该系统包括存储间接分支指令和路径寄存器的高速缓存器。通过路径寄存器和分支指令上的异或运算，在某些分支上更新路径寄存器，然后向寄存器添加一个或多个位。通过对当前指令地址和路径寄存器的一部分执行操作来对高速缓存进行索引; 返回的条目（如果有的话）可以用于预测当前指令的目标。

104. 发明授权

US06553483B1 Enhanced virtual renaming scheme and deadlock prevention therefor 有权
标题翻译：增强的虚拟重命名方案和防止死锁
公开(公告)号：US06553483B1
公开(公告)日：2003-04-22
申请号：US09449520
申请日：1999-11-29
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F938
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated in a processor core.
摘要翻译：在处理器内的增强型虚拟重命名方案中，可以将多个逻辑寄存器映射到单个物理寄存器。值缓存确定根据程序指令生成的新值是否与先前执行的指令相关联的值匹配。如果是，则与新执行的指令相关联的逻辑寄存器共享物理寄存器。此外，当在处理器核心中产生来自旧指令的值时，死锁预防措施可以以从“较小的执行指令”中“窃取”物理寄存器的方式集成到寄存器分配单元中。

105. 发明授权

US06549987B1 Cache structure for storing variable length data 有权
公开(公告)号：US06549987B1
公开(公告)日：2003-04-15
申请号：US09713266
申请日：2000-11-16
申请人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
发明人： Lihu Rappoport , Stephan J. Jourdan , Ronny Ronen
IPC分类号： G06F1200
CPC分类号： G06F12/0846 , G06F12/0875 , G06F12/0886
摘要： A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.

106. 发明授权

US06505293B1 Register renaming to optimize identical register values 失效
标题翻译：注册重命名以优化相同的寄存器值
公开(公告)号：US06505293B1
公开(公告)日：2003-01-07
申请号：US09348973
申请日：1999-07-07
申请人： Stephan J. Jourdan , Ronny Ronen , Adi Yoaz
发明人： Stephan J. Jourdan , Ronny Ronen , Adi Yoaz
IPC分类号： G06F938
CPC分类号： G06F9/30032 , G06F9/383 , G06F9/3834 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A processor architecture for providing many-to-one mappings between logical registers and physical registers, so that more than one logical register may map to the same physical register. Each physical register has an associated counter to indicate whether the physical register is free. A counter is incremented each time a mapping is made to its associated physical register, and is decremented when that mapping is no longer needed. If a logical register named in a decoded instruction is predicted to have the same value as a value stored in a physical register, then the logical register is mapped to the physical register.
摘要翻译：一种用于在逻辑寄存器和物理寄存器之间提供多对一映射的处理器架构，使得多于一个逻辑寄存器可映射到相同的物理寄存器。每个物理寄存器都有一个关联的计数器，用于指示物理寄存器是否空闲。每当对其相关联的物理寄存器进行映射时，计数器递增，并且当不再需要该映射时递减计数器。如果预测在解码指令中命名的逻辑寄存器具有与存储在物理寄存器中的值相同的值，则逻辑寄存器被映射到物理寄存器。

107. 发明授权

US06412050B1 Memory record update filtering 失效
标题翻译：内存记录更新过滤
公开(公告)号：US06412050B1
公开(公告)日：2002-06-25
申请号：US09475984
申请日：1999-12-30
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F1200
CPC分类号： G06F9/3806 , G06F12/126
摘要： Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.
摘要翻译：用于过滤内存记录更新的设备和方法。微处理器可以包括存储器记录更新过滤器。存储器记录更新过滤器可以包括由多个数据条目填充的表存储器。每个数据条目可以包括用于存储数据标签的数据标签字段，用于存储数据值的数据字段和用于存储过滤器值的过滤器字段。第一比较器可以与表存储器的数据标签字段进行通信，以及数据访问信息输入以执行数据标签比较。第二比较器可以与表存储器的滤波器字段进行通信，并且与数据值输入通信。控制电路可以与表存储器，第一比较器和第二比较器通信。

108. 发明授权

US5790822A Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor 失效
标题翻译：用于在流水线微处理器中提供重新排序的指令高速缓存的方法和装置
公开(公告)号：US5790822A
公开(公告)日：1998-08-04
申请号：US621136
申请日：1996-03-21
申请人： Gad S. Sheaffer , Ronny Ronen
发明人： Gad S. Sheaffer , Ronny Ronen
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3853
摘要： A method and apparatus for executing instructions in a pipelined microprocessor. The method includes re-ordering the set of instructions prior to loading the instructions into an instruction cache. In one embodiment, a re-ordering unit receives the set of instructions as a trace segment made of a set of basic blocks of instructions in a logical order of execution. After being re-ordered, the instructions are presented to the reordered instruction cache in bundles. When an instruction is unavailable, possibly due to an unresolved data dependency, no operation codes (nops) are inserted into the bundle in place of an in place of an instruction, creating fixed length bundles. In a second embodiment, nops are not used. Variable length bundles are produced by using an additional bit(s) per instruction to mark the end of the bundles.
摘要翻译：一种用于在流水线微处理器中执行指令的方法和装置。该方法包括在将指令加载到指令高速缓存之前重新排序指令集。在一个实施例中，重新排序单元以逻辑执行顺序作为由一组基本指令块构成的跟踪段来接收指令集。重新排序后，指令将以捆绑形式呈现给重新排序的指令缓存。当指令不可用时，可能由于未解决的数据依赖关系，代替指令，不会将任何操作代码（nops）插入到bundle中，从而创建固定长度的bundle。在第二实施例中，不使用nop。通过使用每个指令的附加位来标记捆绑的末尾来产生可变长度束。

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