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101. 发明申请

US20110210382A1 DIGITAL RADIOGRAPHIC FLAT-PANEL IMAGING ARRAY WITH DUAL HEIGHT SEMICONDUCTOR AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有双高精度半导体的数字放射平面成像阵列及其制造方法
公开(公告)号：US20110210382A1
公开(公告)日：2011-09-01
申请号：US13104999
申请日：2011-05-11
申请人： Timothy J. Tredwell , Jackson Lai
发明人： Timothy J. Tredwell , Jackson Lai
IPC分类号： H01L31/14
CPC分类号： H01L27/14601 , H01L31/1896 , Y02E10/50
摘要： Method of manufacturing imaging arrays can include providing a silicon tile having a first surface and a second, opposite surface. A buried dielectric layer is formed in the silicon tile between the first and second surfaces to define a bottom silicon layer between the first surface and the dielectric layer. A separation boundary is formed in the silicon tile between the second surface and the dielectric layer to define a top silicon layer between the dielectric layer and the separation boundary and a removable silicon layer between the separation boundary and the second surface. An oxide layer formed on the first surface of the silicon tile and the silicon tile is bonded to a glass substrate at the oxide layer. The silicon tile is separated at the separation boundary to remove the removable silicon layer, exposing the top silicon layer. Semiconductive elements are formed using the exposed top silicon layer.
摘要翻译：制造成像阵列的方法可以包括提供具有第一表面和第二相对表面的硅砖。在第一和第二表面之间的硅瓦片中形成掩埋介质层，以在第一表面和介电层之间限定底部硅层。在第二表面和电介质层之间的硅砖中形成分离边界，以在电介质层和分离边界之间限定顶部硅层，以及在分离边界和第二表面之间的可移除的硅层。形成在硅砖的第一表面上的氧化物层和硅砖在氧化物层处接合到玻璃基板。硅片在分离边界处分离以除去可移除的硅层，暴露出顶层硅层。使用暴露的顶部硅层形成半导体元件。

102. 发明授权

US07968358B2 Digital radiographic flat-panel imaging array with dual height semiconductor and method of making same 失效
标题翻译：具有双高度半导体的数字射线照相平板成像阵列及其制造方法
公开(公告)号：US07968358B2
公开(公告)日：2011-06-28
申请号：US12511119
申请日：2009-07-29
申请人： Timothy J. Tredwell , Jackson Lai
发明人： Timothy J. Tredwell , Jackson Lai
IPC分类号： H01L21/00
CPC分类号： H01L27/14601 , H01L31/1896 , Y02E10/50
摘要： A method of manufacturing an imaging array includes providing a silicon tile having a first surface and a second, opposite surface. A buried dielectric layer is formed in the silicon tile between the first and second surfaces to define a bottom silicon layer between the first surface and the dielectric layer. A separation boundary is formed in the silicon tile between the second surface and the dielectric layer to define a top silicon layer between the dielectric layer and the separation boundary and a removable silicon layer between the separation boundary and the second surface. An oxide layer is formed on the first surface of the silicon tile and the silicon tile is bonded to a glass substrate at the oxide layer. The silicon tile is separated at the separation boundary to remove the removable silicon layer, exposing the top silicon layer. Semiconductive elements are formed using the exposed top silicon layer.
摘要翻译：制造成像阵列的方法包括提供具有第一表面和第二相对表面的硅砖。在第一和第二表面之间的硅瓦片中形成掩埋介质层，以在第一表面和介电层之间限定底部硅层。在第二表面和电介质层之间的硅砖中形成分离边界，以在电介质层和分离边界之间限定顶部硅层，以及在分离边界和第二表面之间的可移除的硅层。在硅砖的第一表面上形成氧化物层，并且在氧化物层处将硅瓦贴合到玻璃基板上。硅片在分离边界处分离以除去可移除的硅层，暴露出顶层硅层。使用暴露的顶部硅层形成半导体元件。

103. 发明授权

US07902512B1 Coplanar high fill factor pixel architecture 有权
标题翻译：共面高填充因子像素架构
公开(公告)号：US07902512B1
公开(公告)日：2011-03-08
申请号：US12630959
申请日：2009-12-04
申请人： Jeff Hsin Chang , Timothy J. Tredwell , Gregory N. Heiler
发明人： Jeff Hsin Chang , Timothy J. Tredwell , Gregory N. Heiler
IPC分类号： G01T1/24
CPC分类号： H01L27/14658 , H01L27/14603 , H01L27/14609 , H01L27/14612 , H01L27/14636 , H01L27/14659 , H01L31/022408
摘要： A pixel comprising a scan line proximate to a first surface of a substrate and a bias line between the first surface of the substrate and a first terminal of a photosensing element, where a portion of the bias line is substantially parallel to the scan line. The pixel can also comprise a switching element proximate to the first surface of the substrate and aligned with at least a portion of the scan line. The pixel can include the photosensing element proximate to the first surface of the substrate and aligned with at least a portion of the bias line.
摘要翻译：包括靠近衬底的第一表面的扫描线和在衬底的第一表面和光敏元件的第一端之间的偏置线的像素，其中偏置线的一部分基本上平行于扫描线。像素还可以包括靠近衬底的第一表面并与扫描线的至少一部分对准的开关元件。像素可以包括靠近衬底的第一表面的光敏元件并且与偏置线的至少一部分对准。

104. 发明申请

US20110024774A1 DIGITAL RADIOGRAPHIC FLAT-PANEL IMAGING ARRAY WITH DUAL HEIGHT SEMICONDUCTOR AND METHOD OF MAKING SAME 失效
标题翻译：具有双高精度半导体的数字放射平面成像阵列及其制造方法
公开(公告)号：US20110024774A1
公开(公告)日：2011-02-03
申请号：US12511119
申请日：2009-07-29
申请人： Timothy J. Tredwell , Jackson Lai
发明人： Timothy J. Tredwell , Jackson Lai
IPC分类号： H01L33/00
CPC分类号： H01L27/14601 , H01L31/1896 , Y02E10/50
摘要： A method of manufacturing an imaging array includes providing a silicon tile having a first surface and a second, opposite surface. A buried dielectric layer is formed in the silicon tile between the first and second surfaces to define a bottom silicon layer between the first surface and the dielectric layer. A separation boundary is formed in the silicon tile between the second surface and the dielectric layer to define a top silicon layer between the dielectric layer and the separation boundary and a removable silicon layer between the separation boundary and the second surface. An oxide layer is formed on the first surface of the silicon tile and the silicon tile is bonded to a glass substrate at the oxide layer. The silicon tile is separated at the separation boundary to remove the removable silicon layer, exposing the top silicon layer. Semiconductive elements are formed using the exposed top silicon layer.
摘要翻译：制造成像阵列的方法包括提供具有第一表面和第二相对表面的硅砖。在第一和第二表面之间的硅瓦片中形成掩埋介质层，以在第一表面和介电层之间限定底部硅层。在第二表面和电介质层之间的硅砖中形成分离边界，以在电介质层和分离边界之间限定顶部硅层，以及在分离边界和第二表面之间的可移除的硅层。在硅砖的第一表面上形成氧化物层，并且在氧化物层处将硅瓦贴合到玻璃基板上。硅片在分离边界处分离以除去可移除的硅层，暴露出顶层硅层。使用暴露的顶部硅层形成半导体元件。

105. 发明授权

US07879691B2 Low cost die placement 有权
标题翻译：低成本裸片放置
公开(公告)号：US07879691B2
公开(公告)日：2011-02-01
申请号：US12236972
申请日：2008-09-24
申请人： Roger S. Kerr , Timothy J. Tredwell , Seung-Ho Baek
发明人： Roger S. Kerr , Timothy J. Tredwell , Seung-Ho Baek
IPC分类号： H01L21/00
CPC分类号： H01L24/81 , H01L21/32055 , H01L21/56 , H01L2221/68322 , H01L2221/6835 , H01L2221/68354 , H01L2221/68368 , H01L2221/68372 , H01L2224/16 , H01L2224/7565 , H01L2224/81001 , H01L2224/812 , H01L2224/81201 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01057 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/0401
摘要： Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an SOI (silicon on insulator) wafer and/or an intermediate transfer member. In other embodiments, the release member can be used for a low cost placement of the IC elements in combination with a release wafer.
摘要翻译：示例性实施例提供了使用具有相变材料的释放构件来组装诸如集成电路（IC）芯片的电子设备的方法和系统。具体地说，可以通过引入相变材料的相变来在IC芯片的组装过程中以可缩放的方式选择性地接收，存储，检查，检查和/或释放IC元件/部件。释放构件可以是柔性的或刚性的。在一些实施例中，释放构件可用于与SOI（绝缘体上硅）晶片和/或中间转印构件组合的IC元件的低成本放置。在其他实施例中，释放构件可用于与释放晶片组合的IC元件的低成本放置。

106. 发明申请

US20100320556A1 CONTINUOUS LARGE AREA IMAGING AND DISPLAY ARRAYS USING READOUT ARRAYS FABRICATED IN SILICON-ON-GLASS SUBSTRATES 失效
标题翻译：连续的大面积成像和显示阵列使用在硅玻璃基板上制作的读数阵列
公开(公告)号：US20100320556A1
公开(公告)日：2010-12-23
申请号：US12488074
申请日：2009-06-19
申请人： Timothy J. Tredwell
发明人： Timothy J. Tredwell
IPC分类号： H01L31/0248 , H01L21/77
CPC分类号： H01L31/101 , H01L27/14632 , H01L27/14663 , H01L27/14687 , H01L31/115
摘要： A vertically-integrated image sensor is proposed with the performance characteristics of single crystal silicon but with the area coverage and cost of arrays fabricated on glass. The image sensor can include a backplane array having readout elements implemented in silicon-on-glass, a frontplane array of photosensitive elements vertically integrated above the backplane, and an interconnect layer disposed between the backplane array and the image sensing array. Since large area silicon-on-glass backplanes are formed by tiling thin single-crystal silicon layers cleaved from a thick silicon wafer side-by-side on large area glass gaps between the tiled silicon backplane would normally result in gaps in the image captured by the array. Therefore, embodiments further propose that the pixel pitch in both horizontal and vertical directions of the frontplane be larger than the pixel pitch of the backplane, with the pixel pitch difference being sufficient that the frontplane bridges the gap between backplane tiles.
摘要翻译：提出了一种垂直集成的图像传感器，其具有单晶硅的性能特性，但具有在玻璃上制造的阵列的面积覆盖和成本。图像传感器可以包括具有实现在玻璃上玻璃上的读出元件的背板阵列，垂直集成在背板上方的感光元件的前平面阵列，以及布置在背板阵列和图像感测阵列之间的互连层。由于大面积的硅玻璃背板是通过在平铺的硅背板之间的大面积玻璃间隙上平铺从厚硅晶片并排分离的薄的单晶硅层而形成的，通常会导致图像中的间隙阵列。因此，实施例进一步提出，前平面的水平和垂直方向上的像素间距大于背板的像素间距，像素间距差足以使前平面桥接背板瓦片之间的间隙。

107. 发明申请

US20100129965A1 METAL SUBSTRATE HAVING ELECTRONIC DEVICES FORMED THEREON 失效
公开(公告)号：US20100129965A1
公开(公告)日：2010-05-27
申请号：US12694471
申请日：2010-01-27
申请人： Roger S. Kerr , Timothy J. Tredwell , Mark A. Harland
发明人： Roger S. Kerr , Timothy J. Tredwell , Mark A. Harland
IPC分类号： H01L21/334
CPC分类号： H01L27/1266 , H01L27/1214 , H01L29/78603 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155
摘要： A method of forming an electronic device on a metal substrate deposits a first seed layer of a first metal on at least one master surface with a roughness less than 400 nm. A supporting metal layer is bonded to the first seed layer to form the metal substrate 10. The metal substrate is removed from the master surface, and at least one electronic device is formed on the seed layer of the metal substrate.

108. 发明申请

US20100129945A1 METAL SUBSTRATE HAVING ELECTRONIC DEVICES FORMED THEREON 失效
标题翻译：具有其形成的电子器件的金属基底
公开(公告)号：US20100129945A1
公开(公告)日：2010-05-27
申请号：US12694490
申请日：2010-01-27
申请人： Roger S. Kerr , Timothy J. Tredwell , Mark A. Harland
发明人： Roger S. Kerr , Timothy J. Tredwell , Mark A. Harland
IPC分类号： H01L21/50 , H01L33/00
CPC分类号： H01L27/1266 , H01L27/1214 , H01L29/78603 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155
摘要： A method of forming an electronic device on a metal substrate deposits a first seed layer of a first metal on at least one master surface with a roughness less than 400 nm. A supporting metal layer is bonded to the first seed layer to form the metal substrate 10. The metal substrate is removed from the master surface, and at least one electronic device is formed on the seed layer of the metal substrate.
摘要翻译：在金属基底上形成电子器件的方法在第一金属的第一晶种层上沉积至少一个粗糙度小于400nm的母体表面。将支撑金属层接合到第一种子层以形成金属基板10.金属基板从主表面去除，并且至少一个电子器件形成在金属基板的籽晶层上。

109. 发明申请

US20100128450A1 SOLVENT SOFTENING TO ALLOW DIE PLACEMENT 审中-公开
标题翻译：解决方案要保证放置
公开(公告)号：US20100128450A1
公开(公告)日：2010-05-27
申请号：US12696307
申请日：2010-01-29
申请人： Roger S. Kerr , Timothy J. Tredwell , Seung-Ho Baek
发明人： Roger S. Kerr , Timothy J. Tredwell , Seung-Ho Baek
IPC分类号： H05K1/18
CPC分类号： H01L24/82 , H01L21/56 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2221/68363 , H01L2223/6677 , H01L2224/04105 , H01L2224/18 , H01L2224/76155 , H01L2224/82102 , H01L2224/97 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/09701 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/82
摘要： Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, by selectively and seating IC elements onto/into a receiving substrate, such as a chip substrate. Specifically, the assembly of IC chips can include embedding IC elements onto the receiving substrate upon softening the receiving substrate. Such softening can be performed by using a softening agent and/or an activatable thermal barrier material. In an exemplary embodiment, pockets can be formed in the receiving substrate using the activatable thermal barrier material for the IC assembly.
摘要翻译：示例性实施例提供了通过选择性地将IC元件放置到接收基板（例如芯片基板）上来组装诸如集成电路（IC）芯片的电子器件的方法和系统。具体来说，IC芯片的组装可以包括在接收基板软化时将IC元件嵌入到接收基板上。这种软化可以通过使用软化剂和/或可激活的热障材料来进行。在示例性实施例中，可以使用用于IC组件的可激活热障材料在接收衬底中形成袋。

110. 发明申请

US20100075459A1 THERMAL BARRIER LAYER FOR INTEGRATED CIRCUIT MANUFACTURE 有权
标题翻译：用于集成电路制造的热障板
公开(公告)号：US20100075459A1
公开(公告)日：2010-03-25
申请号：US12236907
申请日：2008-09-24
申请人： Roger S. Kerr , Timothy J. Tredwell , Seung-Ho Baek
发明人： Roger S. Kerr , Timothy J. Tredwell , Seung-Ho Baek
IPC分类号： H01L21/50 , H01L21/67
CPC分类号： H01L24/83 , H01L21/6835 , H01L24/19 , H01L24/29 , H01L24/82 , H01L24/97 , H01L2221/68354 , H01L2221/68363 , H01L2221/68368 , H01L2223/6677 , H01L2224/04105 , H01L2224/16 , H01L2224/16227 , H01L2224/2919 , H01L2224/29298 , H01L2224/7565 , H01L2224/76155 , H01L2224/7665 , H01L2224/81005 , H01L2224/81143 , H01L2224/82102 , H01L2224/83192 , H01L2224/838 , H01L2224/97 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01077 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/14 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10T29/53178 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/0401
摘要： Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, by selectively and scalably embedding or seating IC elements onto/into a receiving substrate, such as a chip substrate. Preparing of the chip substrate can be performed by depositing or patterning an activatable thermal barrier material on a surface of the substrate. The IC chips are secured on the prepared substrate by activating the thermal barrier material between the chip substrate and IC chips. Securing can include softening of the chip substrate with the activated thermal barrier material to an amount suitable for embedding the IC chips. Securing can also include adhesively bonding the IC chips to the substrate with the activated thermal barrier material in the case of a non-pliable substrate.
摘要翻译：示例性实施例提供了用于通过有选择地和可扩展地将IC元件嵌入或放置到接收基板（例如芯片基板）上的诸如集成电路（IC）芯片之类的电子装置的组装方法和系统。可以通过在基板的表面上沉积或图案化可激活的热障材料来进行芯片基板的制备。通过激活芯片衬底和IC芯片之间的热障材料，将IC芯片固定在制备的衬底上。固定可以包括利用活化的热障材料将芯片基板软化到适于嵌入IC芯片的量。在非柔性基板的情况下，固定还可以包括将IC芯片与激活的热障材料粘合到基板上。

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