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    • 108. 发明申请
    • MEASURING APPARATUS, TESTING APPARATUS, AND ELECTRONIC DEVICE
    • 测量装置,测试装置和电子装置
    • US20080040060A1
    • 2008-02-14
    • US11623101
    • 2007-01-15
    • Harry HouTakahiro Yamaguchi
    • Harry HouTakahiro Yamaguchi
    • G06F19/00G06F15/00
    • G01R31/31725G01R31/31937
    • A measuring apparatus that measures signal-under-test of which signal level is changed at a predetermined bit time interval is provided. The measuring apparatus includes: a strobe timing generator that sequentially generates strobes arranged at substantially even time intervals; a level comparison section that detects the level of the signal-under-test at a timing at which each strobe is sequentially provided; a capture memory that stores therein the signal level outputted by the level comparison section; and a digital signal processing section that calculates a measurement result of the signal-under-test based on data series including data which have substantially even time intervals and each of which interval is larger than a bit time interval of the signal-under-test. The measuring apparatus may include a logical comparison section that outputs a comparison result indicating whether the logical value detected by the level comparison section is corresponding to an expected value and a memory that stores therein the comparison result outputted by the logical comparison section instead of the capture memory. In this case, the digital signal processing section derives the measurement result of the signal-under-test from the comparison result stored in the memory.
    • 提供测量信号电平以预定位时间间隔改变的测试信号的测量装置。 测量装置包括:选通定时发生器,其顺序地产生以基本均匀的时间间隔布置的选通; 电平比较部,其在顺序提供每个频闪的定时检测被测信号的电平; 捕获存储器,其中存储由所述电平比较部分输出的信号电平; 以及数字信号处理部,其基于包括具有基本上均匀的时间间隔并且每个间隔大于被测信号的位时间间隔的数据的数据序列来计算待测信号的测量结果。 测量装置可以包括逻辑比较部分,其输出指示由电平比较部分检测到的逻辑值是否对应于预期值的比较结果,以及存储器,其中存储由逻辑比较部分输出的比较结果,而不是捕获 记忆。 在这种情况下,数字信号处理部根据存储在存储器中的比较结果导出测试信号的测量结果。
    • 110. 发明授权
    • Test apparatus and test method for testing a device under test
    • 用于测试被测设备的测试设备和测试方法
    • US07313496B2
    • 2007-12-25
    • US11056330
    • 2005-02-11
    • Masahiro IshidaTakahiro YamaguchiMani Soma
    • Masahiro IshidaTakahiro YamaguchiMani Soma
    • G01D3/00G01R27/28
    • G01R31/31709G01R31/2882G01R31/31716
    • A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.
    • 用于测试被测设备(DUT)的测试设备包括一个性能板; 用于产生用于测试DUT的测试信号和根据DUT输出的输出信号确定DUT的通过/失败的主框架; 在主框架和执行板之间的引脚电子设备,并在主框架和DUT之间执行发送和接收信号; 确定性抖动注入单元,用于在不通过引脚电子装置的情况下接收输出信号,并将作为所注入的确定性抖动的接收输出信号的环路信号输入到DUT的输入引脚,而不通过引脚电子器件; 以及用于确定DUT的输入引脚是否具有由引脚电子器件输出的测试信号或由确定性抖动注入单元输出的环路信号的开关单元。