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101. 发明申请

US20050110072A1 Precise patterning of high-K films 审中-公开
公开(公告)号：US20050110072A1
公开(公告)日：2005-05-26
申请号：US11018015
申请日：2004-12-20
申请人： Justin Brask , Mark Doczy , Matthew Metz , John Barnak , Paul Markworth
发明人： Justin Brask , Mark Doczy , Matthew Metz , John Barnak , Paul Markworth
IPC分类号： H01L21/3063 , H01L21/28 , H01L21/311 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/28123 , H01L21/31111
摘要： A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

102. 发明申请

US20050148137A1 Nonplanar transistors with metal gate electrodes 有权
标题翻译：具有金属栅电极的非平面晶体管
公开(公告)号：US20050148137A1
公开(公告)日：2005-07-07
申请号：US10750061
申请日：2003-12-30
申请人： Justin Brask , Brian Doyle , Mark Doczy , Robert Chau
发明人： Justin Brask , Brian Doyle , Mark Doczy , Robert Chau
IPC分类号： H01L21/336 , H01L21/77 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L29/49 , H01L29/786
CPC分类号： H01L29/785 , H01L21/823821 , H01L21/823828 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L29/4908 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：一种半导体器件，包括半导体本体，该半导体本体具有形成在绝缘衬底上的顶表面和第一和第二横向相对的侧壁。在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。栅电极包括直接与栅介电层相邻形成的金属膜。一对源极和漏极区域在栅电极的相对侧的半导体本体中是均匀的。

103. 发明申请

US20070145468A1 Quantum dot nonvolatile transistor 审中-公开
标题翻译：量子点非易失性晶体管
公开(公告)号：US20070145468A1
公开(公告)日：2007-06-28
申请号：US11322089
申请日：2005-12-28
申请人： Amlan Majumdar , Suman Datta , Been-Yih Jin , Mark Doczy , Robert Chau
发明人： Amlan Majumdar , Suman Datta , Been-Yih Jin , Mark Doczy , Robert Chau
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , B82Y10/00 , H01L27/115 , H01L29/40114 , H01L29/42332 , H01L29/66825
摘要： Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.
摘要翻译：本发明的一些实施例包括与非易失性存储晶体管相关的装置和方法。

104. 发明申请

US20050156171A1 Nonplanar transistors with metal gate electrodes 有权
公开(公告)号：US20050156171A1
公开(公告)日：2005-07-21
申请号：US11023881
申请日：2004-12-27
申请人： Justin Brask , Brian Doyle , Mark Doczy , Robert Chau
发明人： Justin Brask , Brian Doyle , Mark Doczy , Robert Chau
IPC分类号： H01L21/336 , H01L21/77 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L29/49 , H01L29/786 , H01L29/94
CPC分类号： H01L29/785 , H01L21/823821 , H01L21/823828 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L29/4908 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

105. 发明申请

US20080090397A1 Nonplanar transistors with metal gate electrodes 有权
标题翻译：具有金属栅电极的非平面晶体管
公开(公告)号：US20080090397A1
公开(公告)日：2008-04-17
申请号：US11986510
申请日：2007-11-21
申请人： Justin Brask , Brian Dovle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
发明人： Justin Brask , Brian Dovle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
IPC分类号： H01L21/3205
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/41791 , H01L29/66439 , H01L29/66545 , H01L29/66795 , Y10S438/926 , Y10S438/974
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。栅电极包括直接与栅介电层相邻形成的金属膜。然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

106. 发明申请

US20060138553A1 Nonplanar transistors with metal gate electrodes 有权
公开(公告)号：US20060138553A1
公开(公告)日：2006-06-29
申请号：US11362453
申请日：2006-02-24
申请人： Justin Brask , Brian Doyle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
发明人： Justin Brask , Brian Doyle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/41791 , H01L29/66439 , H01L29/66545 , H01L29/66795 , Y10S438/926 , Y10S438/974
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

107. 发明授权

US06998686B2 Metal-gate electrode for CMOS transistor applications 失效
标题翻译：用于CMOS晶体管应用的金属栅电极
公开(公告)号：US06998686B2
公开(公告)日：2006-02-14
申请号：US10230944
申请日：2002-08-28
申请人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
发明人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.
摘要翻译：描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。栅电极结构具有三层金属栅电极和多晶硅层。第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。第二金属层用于设定栅电极结构的功函数。第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。

108. 发明申请

US20060017122A1 Novel metal-gate electrode for CMOS transistor applications 有权
公开(公告)号：US20060017122A1
公开(公告)日：2006-01-26
申请号：US11231437
申请日：2005-09-20
申请人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
发明人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

109. 发明授权

US06696345B2 Metal-gate electrode for CMOS transistor applications 有权
标题翻译：用于CMOS晶体管应用的金属栅电极
公开(公告)号：US06696345B2
公开(公告)日：2004-02-24
申请号：US10041539
申请日：2002-01-07
申请人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
发明人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
IPC分类号： H01R424
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.
摘要翻译：描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。栅电极结构具有三层金属栅电极和多晶硅层。第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。第二金属层用于设定栅电极结构的功函数。第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。制造栅极电极结构的方法包括形成足够厚的三个金属层，以使得每个层提供屏障和所述功能设定功能而且还足够薄以使得可以进行随后的湿蚀刻而没有金属层的过度底切。在注入和退火工艺期间，多晶硅层用作金属层上的保护掩模，以保护底层硅衬底与植入过程中使用的掺杂剂相互作用。

110. 发明授权

US07936025B2 Metalgate electrode for PMOS transistor 有权
标题翻译：用于PMOS晶体管的金属栅电极
公开(公告)号：US07936025B2
公开(公告)日：2011-05-03
申请号：US11231437
申请日：2005-09-20
申请人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
发明人： Robert Chau , Mark Doczy , Brian Doyle , Jack Kavalieros
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.
摘要翻译：描述了具有多层栅电极结构的CMOS晶体管结构和制造方法。栅电极结构具有三层金属栅电极和多晶硅层。第一金属层用作阻挡层以防止第二金属层与下面的电介质反应。第二金属层用于设定栅电极结构的功函数。第三金属层用作阻挡第二金属层与多晶硅层反应的屏障。

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