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    • 110. 发明授权
    • State retention within a data processing system
    • 在数据处理系统中保留状态
    • US07183825B2
    • 2007-02-27
    • US10818861
    • 2004-04-06
    • Milind P. PadhyeChristopher K. Y. ChunYuan YuanSanjay Gupta
    • Milind P. PadhyeChristopher K. Y. ChunYuan YuanSanjay Gupta
    • H03K3/289
    • G11C5/147
    • Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.
    • 通过使用从电路块或电路块的一部分去除功率的功率门控,可以降低功耗,以减少漏电流。 一个实施例使用修改的状态保持触发器,其能够在电力被去除或部分地从电路中移除时保持状态。 另一实施例使用修改状态保持缓冲器,其能够在电力被去除或部分地从电路中移除时保持状态。 状态保持触发器和缓冲器可以用于允许状态保持同时仍然减少漏电流。 还公开了使用例如状态保持触发器和缓冲器来降低功率和保持状态的各种方法。 例如,软件,硬件或软件和硬件方法的组合可以用于在保持状态的同时进入深度睡眠或空闲模式。