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101. 发明授权

US08350358B2 Techniques for placement of active and passive devices within a chip 有权
标题翻译：有源和无源器件放置在芯片内的技术
公开(公告)号：US08350358B2
公开(公告)日：2013-01-08
申请号：US13231084
申请日：2011-09-13
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L29/00
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要翻译：半导体管芯包括具有第一和第二侧面的半导体衬底层，与半导体衬底层的第二侧相邻的金属层，在半导体衬底层的第一侧上的有源层中的一个或多个有源器件; 以及与有源层电连通的金属层中的无源器件。无源器件可以通过硅通孔（TSV）电耦合到有源层。

102. 发明授权

US08294240B2 Through silicon via with embedded decoupling capacitor 有权
标题翻译：通过硅通孔与嵌入式去耦电容
公开(公告)号：US08294240B2
公开(公告)日：2012-10-23
申请号：US12479885
申请日：2009-06-08
申请人： Matthew Michael Nowak , Shiqun Gu
发明人： Matthew Michael Nowak , Shiqun Gu
IPC分类号： H01L29/92
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/642 , H01L28/60 , H01L2223/6616 , H01L2223/6622 , H01L2224/0557 , H01L2224/06181 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2224/05552
摘要： A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die.
摘要翻译：具有基板的半导体管芯包括硅通孔。贯通硅通孔包括具有第一同轴导体，第二同轴导体和将第一同轴导体与第二同轴导体分离的同轴电介质的去耦电容器。去耦电容器被配置为为半导体管芯上的部件提供局部电荷存储。

103. 发明申请

US20120248582A1 Voltage Switchable Dielectric for Die-Level Electrostatic Discharge (ESD) Protection 有权
标题翻译：用于芯片级静电放电（ESD）保护的电压可切换介质
公开(公告)号：US20120248582A1
公开(公告)日：2012-10-04
申请号：US13078672
申请日：2011-04-01
申请人： Shiqun Gu , Ratibor Radojcic , Yiming Li
发明人： Shiqun Gu , Ratibor Radojcic , Yiming Li
IPC分类号： H01L23/58 , H01L21/50 , H01L21/31
CPC分类号： H01L23/62 , H01L23/29 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.
摘要翻译：可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端，而不会流过电流通过电路的电路。因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。

104. 发明授权

US08143952B2 Three dimensional inductor and transformer 有权
标题翻译：三维电感和变压器
公开(公告)号：US08143952B2
公开(公告)日：2012-03-27
申请号：US12576033
申请日：2009-10-08
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/14
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中。

105. 发明申请

US20110248405A1 Selective Patterning for Low Cost through Vias 审中-公开
标题翻译：通过Vias实现低成本的选择性图案化
公开(公告)号：US20110248405A1
公开(公告)日：2011-10-13
申请号：US12757570
申请日：2010-04-09
申请人： Yiming Li , Mario Francisco Velez , Shiqun Gu
发明人： Yiming Li , Mario Francisco Velez , Shiqun Gu
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H05K3/002 , H01L21/486 , H01L21/76898 , H01L23/15 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K3/386 , H05K2201/0394 , H01L2924/00
摘要： A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.
摘要翻译：在沉积金属线和蚀刻通孔之前沉积在基板上的阻挡层使用各向同性蚀刻工艺可以在基板中实现通孔中的通孔的低成本制造。例如，可以使用玻璃基板的湿式蚀刻来通过玻璃基板进行制造，而不会从玻璃基板上的湿法蚀刻短路金属线上进行底切。阻挡层防止衬底上的导电层与衬底上的多于一条金属线的接触。制造过程允许在诸如玻璃基板的基板上堆叠设备并且将设备与通孔连接。

106. 发明申请

US20110193212A1 Systems and Methods Providing Arrangements of Vias 审中-公开
标题翻译：系统和方法提供安排通风口
公开(公告)号：US20110193212A1
公开(公告)日：2011-08-11
申请号：US12701642
申请日：2010-02-08
申请人： Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
发明人： Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5286 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05093 , H01L2224/13009 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/14505 , H01L2224/16145 , H01L2224/16146 , H01L2224/17517 , H01L2224/48091 , H01L2224/48227 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.
摘要翻译：半导体芯片包括电连接阵列和将半导体芯片中的至少一个电路耦合到电接触阵列的多个通孔。电触点阵列的电触点中的第一个耦合到N个通孔，并且电触点阵列的电触点中的第二个耦合到M个通孔。 M和N是不同值的正整数。

107. 发明申请

US20110042829A1 IC Interconnect 有权
标题翻译： IC互连
公开(公告)号：US20110042829A1
公开(公告)日：2011-02-24
申请号：US12938396
申请日：2010-11-03
申请人： Kenneth Kaskoun , Shiqun Gu , Bart Swinnen
发明人： Kenneth Kaskoun , Shiqun Gu , Bart Swinnen
IPC分类号： H01L23/538
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/06181 , H01L2924/0002 , H01L2924/00
摘要： A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.
摘要翻译：多层IC器件包含第一裸片，其包括具有第一组和第二组通孔的衬底。第一组通孔从衬底的一侧延伸，并且第二组通孔从衬底的相对侧延伸。两组通孔耦合在一起。第一组通孔在物理上小于第二组通孔。具有一组互连件的第二管芯相对于第一管芯堆叠，其中互连件耦合到第一组通孔。

108. 发明申请

US20100308435A1 Through Silicon Via With Embedded Decoupling Capacitor 有权
标题翻译：通过硅通过嵌入式去耦电容器
公开(公告)号：US20100308435A1
公开(公告)日：2010-12-09
申请号：US12479885
申请日：2009-06-08
申请人： Matthew Michael Nowak , Shiqun Gu
发明人： Matthew Michael Nowak , Shiqun Gu
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L23/642 , H01L28/60 , H01L2223/6616 , H01L2223/6622 , H01L2224/0557 , H01L2224/06181 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2224/05552
摘要： A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die.
摘要翻译：具有基板的半导体管芯包括硅通孔。贯通硅通孔包括具有第一同轴导体，第二同轴导体和将第一同轴导体与第二同轴导体分离的同轴电介质的去耦电容器。去耦电容器被配置为为半导体管芯上的部件提供局部电荷存储。

109. 发明申请

US20100258949A1 Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly 有权
标题翻译：降低3D半导体器件粘合和组装过程中静电放电的敏感性
公开(公告)号：US20100258949A1
公开(公告)日：2010-10-14
申请号：US12421096
申请日：2009-04-09
申请人： Brian M. Henderson , Reza Jalilizeinali , Shiqun Gu
发明人： Brian M. Henderson , Reza Jalilizeinali , Shiqun Gu
IPC分类号： H01L23/52 , H01L21/50 , H05K3/36 , H05K13/00
CPC分类号： H01L23/488 , H01L21/50 , H01L21/67092 , H01L23/60 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513
摘要： A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.
摘要翻译：一种组装堆叠IC器件时降低静电放电敏感性的方法。该方法包括将第一半导体器件的接地平面和第二半导体器件的接地平面耦合到基本上相同的电位。第一半导体器件上的有源电路和第二半导体器件上的有源电路在接地平面耦合之后被电耦合。电耦合第一和第二半导体器件的接地平面产生优选的接地静电放电路径，从而最小化对敏感电路元件的潜在损害。

110. 发明申请

US20100257379A1 Multiple Power Mode System and Method for Memory 有权
标题翻译：多功率模式系统和存储器方法
公开(公告)号：US20100257379A1
公开(公告)日：2010-10-07
申请号：US12417309
申请日：2009-04-02
申请人： Feng Wang , Shiqun Gu
发明人： Feng Wang , Shiqun Gu
IPC分类号： G06F1/00
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/3296 , Y02D10/14 , Y02D10/172
摘要： A memory power management system and method supporting multiple power modes for powering memory channels. The power management system can include a memory controller that controls the memory channel; a throughput detector that detects a requested throughput of the memory channel; a power control logic that determines a desired power mode corresponding to the requested throughput; and a power control device that supplies a desired voltage of the desired power mode to the memory channel. The power management system can include multiple memory controllers for controlling a multi-channel memory independently. The method includes detecting a requested throughput for the memory channel; determining a desired voltage related to the requested throughput; requesting the desired voltage from a voltage device; and applying the desired voltage to the memory channel. In some embodiments, the method only applies the desired voltage if it does not change for a threshold time duration.
摘要翻译：一种支持多种功率模式以为存储器通道供电的存储器电源管理系统和方法。电源管理系统可以包括控制存储器通道的存储器控制器; 吞吐量检测器，其检测所述存储器通道的所请求的吞吐量; 功率控制逻辑，其确定对应于所请求的吞吐量的期望功率模式; 以及功率控制装置，其将期望的功率模式的期望电压提供给存储器通道。电源管理系统可以包括用于独立地控制多通道存储器的多个存储器控制器。所述方法包括检测所述存储器通道的所请求的吞吐量; 确定与所请求的吞吐量相关的期望电压; 从电压装置请求所需的电压; 以及将所需的电压施加到存储器通道。在一些实施例中，如果在阈值持续时间内没有改变，该方法仅施加期望的电压。

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