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101. 发明授权

US08598662B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08598662B2
公开(公告)日：2013-12-03
申请号：US13063745
申请日：2011-03-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803 , H01L29/7849
摘要： A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.
摘要翻译：半导体器件包括：位于绝缘层上的半导体衬底; 以及绝缘体，其位于所述绝缘层上并且嵌入所述半导体衬底中，其中所述绝缘体在其中向所述半导体衬底施加应力。一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在所述半导体衬底内形成空腔以暴露所述绝缘层; 在空腔中形成绝缘体，其中绝缘体在其中向半导体衬底施加应力。它有助于减少短沟道效应，源极/漏极区域的电阻和寄生电容。

102. 发明授权

US08598595B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08598595B2
公开(公告)日：2013-12-03
申请号：US13003873
申请日：2010-09-26
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/7848
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括SOI衬底; 在所述SOI衬底上形成的半导体鳍片，所述半导体鳍片具有彼此相对并在所述SOI衬底的表面上向上并且在所述第二衬底的中心部分处开口的第一侧和第二侧; 侧和第一侧相对; 形成在所述翅片中并且在所述第二侧处在所述第一侧和所述沟槽之间的沟道区域; 源极和漏极区域形成在翅片中并夹着沟道区域; 以及形成在所述SOI衬底上并且邻近所述鳍的所述第一侧的栅极堆叠，其中所述栅极堆叠包括远离所述第一侧延伸并且邻近所述沟道区延伸的第一栅极电介质，所述第一侧并且邻近所述第一栅极电介质延伸，所述第二栅极电介质延伸远离所述第一侧并且横向邻近所述第一导体层的一侧;以及第二导体层，所述第二导体层从所述第一侧延伸并且横向相邻到第二栅极电介质的一侧。本发明的实施例可以应用于制造FinFET。

103. 发明授权

US08587066B2 Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) 失效
标题翻译：具有半导体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的不对称结或反向晕轮廓的结构和方法
公开(公告)号：US08587066B2
公开(公告)日：2013-11-19
申请号：US13407264
申请日：2012-02-28
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

104. 发明申请

US20130299885A1 FINFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： FINFET及其制造方法
公开(公告)号：US20130299885A1
公开(公告)日：2013-11-14
申请号：US13579192
申请日：2012-05-14
申请人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括在半导体衬底上的蚀刻停止层; 在蚀刻停止层上的半导体鳍片; 栅极导体，其在与半导体鳍片的长度方向垂直的方向上延伸并覆盖半导体鳍片的至少两个侧面; 在栅极导体和半导体鳍片之间的栅介质层; 源极区和漏极区，分别设置在半导体鳍的两端; 以及与栅极电介质层下方的蚀刻停止层相邻的层间绝缘层，并且将栅极导体与蚀刻停止层和半导体鳍分离。 FinFET的鳍的高度近似等于用于形成半导体鳍的半导体层的厚度。

105. 发明申请

US20130285157A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130285157A1
公开(公告)日：2013-10-31
申请号：US13988192
申请日：2011-02-26
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/40 , H01L27/088
CPC分类号： H01L29/401 , H01L21/28518 , H01L21/76807 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure comprises: a first interlayer structure having a first dielectric layer and first contact vias; a second interlayer structure having a cap layer and second contact vias; and a third interlayer structure having a second dielectric layer and third contact vias. The first dielectric layer is flush with a gate stack or covers the gate stack, and the first contact vias penetrate through the first dielectric layer and are electrically connected with at least a portion of source/drain regions. The cap layer covers the first interlayer structure, and the second contact vias penetrate through the cap layer and are electrically connected with the first contact vias and the gate stack through a first liner. The second dielectric layer covers the second interlayer structure, and the third contact vias penetrate through the second dielectric layer and are electrically connected with the second contact vias through a second liner.
摘要翻译：半导体结构包括：具有第一介电层和第一接触通孔的第一层间结构; 具有盖层和第二接触通孔的第二层间结构; 以及具有第二介电层和第三接触通孔的第三层间结构。第一电介质层与栅极叠层齐平或覆盖栅极堆叠，并且第一接触通孔穿过第一电介质层并且与源/漏区的至少一部分电连接。盖层覆盖第一层间结构，并且第二接触通孔穿过盖层并且通过第一衬垫与第一接触通孔和栅极堆叠电连接。第二电介质层覆盖第二层间结构，第三接触通孔穿过第二电介质层，并通过第二衬垫与第二接触通孔电连接。

106. 发明申请

US20130276872A1 SOLAR CELL UNIT AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：太阳能电池单元及其制造方法
公开(公告)号：US20130276872A1
公开(公告)日：2013-10-24
申请号：US13864503
申请日：2013-04-17
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L31/0687 , H01L31/18
CPC分类号： H01L31/0687 , H01L31/022425 , H01L31/035281 , H01L31/0443 , H01L31/047 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A solar cell unit comprising a strip plate which has a third surface and a fourth surface opposite to the third surface, wherein a third doping region and a fourth doping region are arranged on the third surface and the fourth surface respectively, and a first doping region and a second doping region are arranged on side surfaces adjacent to the third surface and the fourth surface respectively; the types of impurities in the third doping region and the fourth doping region are contrary to one another; the surfaces of the first doping region and the second doping region have uniform doping type. Accordingly, the present invention further provides a method for manufacturing a solar cell unit.
摘要翻译：一种太阳能电池单元，包括具有第三表面和与第三表面相对的第四表面的带状板，其中第三掺杂区域和第四掺杂区域分别设置在第三表面和第四表面上，并且第一掺杂区域并且第二掺杂区域分别布置在与第三表面和第四表面相邻的侧表面上; 第三掺杂区域和第四掺杂区域中的杂质类型彼此相反; 第一掺杂区域和第二掺杂区域的表面具有均匀的掺杂类型。因此，本发明还提供一种太阳能电池单元的制造方法。

107. 发明授权

US08541293B2 Method of controlled lateral etching 有权
标题翻译：受控横向蚀刻方法
公开(公告)号：US08541293B2
公开(公告)日：2013-09-24
申请号：US13509604
申请日：2011-11-23
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/36 , H01L21/84 , H01L21/00 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/31144 , H01L21/823821 , H01L21/84 , H01L21/845
摘要： A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure.
摘要翻译：公开了一种受控横向蚀刻的方法。在一个实施例中，该方法可以包括：在包括突出结构的第一材料层上形成第二材料层; 在所述第二材料层的与所述突出结构的垂直表面相对的外表面上形成间隔物; 在所述第二材料层和所述间隔物的表面上形成第三材料层; 在所述第三材料层上形成在所述第一材料层的表面的横向方向上延伸的掩模层; 并横向蚀刻布置在突出结构的垂直表面上的各个层的部分。

108. 发明授权

US08470662B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08470662B2
公开(公告)日：2013-06-25
申请号：US13063538
申请日：2010-06-28
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/28176 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a semiconductor device and a manufacturing method for making the same, wherein, according to the method, after the gate stack is formed, a buffer layer is formed on sidewalls of an PMOS gate stack, the buffer layer being formed of a porous low-k dielectric layer; and then, sidewall spacers and source/drain/halo regions, and source and drain regions are formed for the device; and finally, a high-temperature anneal is conducted in an oxygen environment such that the oxygen in the oxygen environment diffuse through the buffer layer into the high-k dielectric layer of the second gate stack. The present invention lowers threshold voltage of the PMOS device without affecting the threshold voltage of the NMOS device, avoids damages to the gate and substrate incurred by removing the PMOS sidewall spacer in a traditional process, and hereby effectively improves the overall performance of the device.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及一种半导体器件及其制造方法，其中，根据该方法，在形成栅极叠层之后，在PMOS栅极叠层的侧壁上形成缓冲层，缓冲层由多孔低k电介质层; 然后为器件形成侧壁间隔物和源极/漏极/晕圈区域以及源极和漏极区域; 最后，在氧环境中进行高温退火，使得氧环境中的氧气通过缓冲层扩散到第二栅极叠层的高k电介质层。本发明降低了PMOS器件的阈值电压，而不影响NMOS器件的阈值电压，避免了在传统工艺中去除PMOS侧壁间隔物对栅极和衬底的损坏，从而有效地提高了器件的整体性能。

109. 发明授权

US08466500B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08466500B2
公开(公告)日：2013-06-18
申请号：US13063977
申请日：2011-02-24
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L33/12
CPC分类号： H01L29/7848 , H01L29/0653 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7849
摘要： The present invention discloses a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor manufacturing. According to the present invention, the semiconductor device comprises: a semiconductor substrate; a gate region located above the semiconductor substrate; S/D regions located at both sides of the gate region and made of a stress material; wherein a concentrated stress region is formed between the gate region and the semiconductor substrate, and the concentrated stress region comprises an upper SOI layer adjacent to the gate region above, and a lower stress release layer adjacent to the semiconductor substrate below. The present invention applies to the manufacturing of a MOSFET.
摘要翻译：本发明公开了一种半导体器件及其制造方法，涉及半导体制造领域。根据本发明，半导体器件包括：半导体衬底; 位于半导体衬底上方的栅极区域; S / D区域位于栅极区域的两侧并由应力材料制成; 其中在所述栅极区域和所述半导体衬底之间形成集中应力区域，并且所述集中应力区域包括与所述栅极区域相邻的上部SOI层以及与所述半导体衬底相邻的较低应力释放层。本发明适用于MOSFET的制造。

110. 发明申请

US20130119484A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130119484A1
公开(公告)日：2013-05-16
申请号：US13063907
申请日：2011-02-27
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/51 , H01L29/40
CPC分类号： H01L29/518 , H01L29/401 , H01L29/4983 , H01L29/66477 , H01L29/78
摘要： The present invention provides a method of manufacturing a semiconductor device comprising: providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially; nitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by the gate; and forming spacers around the gate. Accordingly, the present invention further provides a semiconductor device. Portions of the high-k dielectric layer on the semiconductor substrate, which are not covered by the gate or the spacers positioned thereon, are nitridated, such that an oxygen diffusion barrier layer is formed on the surface of the high-k dielectric layer, thereby oxygen diffusion in the lateral direction into the high-k dielectric layer under the gate is prevented, and the operation performance of the semiconductor device is optimized.
摘要翻译：本发明提供一种制造半导体器件的方法，包括：提供半导体衬底，其上依次形成高k电介质层和图案化栅极; 半导体衬底上未被栅极覆盖的高k电介质层的氮化部分; 并在栅极周围形成间隔物。因此，本发明还提供一种半导体器件。半导体衬底上没有被栅极或位于其上的间隔物覆盖的高k电介质层的部分被氮化，使得在高k电介质层的表面上形成氧扩散阻挡层，从而防止在栅极下的高k电介质层的横向氧扩散，并优化半导体器件的操作性能。

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