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    • 103. 发明申请
    • 2D block processing architecture
    • 2D块处理架构
    • US20050226337A1
    • 2005-10-13
    • US10816391
    • 2004-03-31
    • Mikhail DorojevetsEiji Ogura
    • Mikhail DorojevetsEiji Ogura
    • H04N7/12H04N7/26
    • H04N19/43
    • A video platform architecture for video processing includes complex video compression/decompression algorithms in a computer with a two-dimensional Single-Instruction Multiple-Data (SIMD) array architecture. The video platform architecture includes one or more video processing modules, on-chip shared memory, and a general-purpose RISC central processing unit CPU used as a system controller. Each video processing module includes a rectangular array of processing elements (PEs), a block load/store unit, a global-accumulation unit. Video to be processed is configured into blocks of data, and a general-purpose CPU used as a local controller. A plurality of registers are provided in the processing elements and the block load/store unit to support two-dimensional processing of the data blocks. Types of registers used include block registers, vector registers, scalar registers, and exchange registers. Each of these registers is designed to hold a short ordered one- or two-dimensional set of video data (data blocks). These registers are arranged in a hierarchical configuration along the data flow path between the on-chip memory and processing units within the PE array.
    • 用于视频处理的视频平台架构包括具有二维单指令多数据(SIMD)阵列架构的计算机中的复杂视频压缩/解压缩算法。 视频平台架构包括一个或多个视频处理模块,片上共享存储器以及用作系统控制器的通用RISC中央处理单元CPU。 每个视频处理模块包括处理元件(PE)的矩形阵列,块加载/存储单元,全局累加单元。 要处理的视频被配置为数据块,以及用作本地控制器的通用CPU。 在处理元件和块加载/存储单元中提供多个寄存器以支持数据块的二维处理。 使用的寄存器类型包括块寄存器,向量寄存器,标量寄存器和交换寄存器。 这些寄存器中的每一个被设计成保存短的一维或二维视频数据集(数据块)。 这些寄存器沿着片内存储器和PE阵列内的处理单元之间的数据流路分布配置。