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101. 发明申请

US20060025447A1 Synthesis of 6,7-dihydro-5H-imidazo[1,2-a]imidazole-3-sulfonic acid amides 有权
标题翻译： 6,7-二氢-5H-咪唑并[1,2-a]咪唑-3-磺酸酰胺的合成
公开(公告)号：US20060025447A1
公开(公告)日：2006-02-02
申请号：US11188377
申请日：2005-07-25
申请人： Xiao-Jun Wang , Thomas Wirth , Thomas Nicola , Li Zhang , Rogelio Frutos , Yibo Xu , Dhileopkumar Krishnamurihy , Laurence Nummy , Richard Varsolona , Chris Senanayake , Jutta Kroeber
发明人： Xiao-Jun Wang , Thomas Wirth , Thomas Nicola , Li Zhang , Rogelio Frutos , Yibo Xu , Dhileopkumar Krishnamurihy , Laurence Nummy , Richard Varsolona , Chris Senanayake , Jutta Kroeber
IPC分类号： A61K31/454 , A61K31/4188 , C07D487/04
CPC分类号： C07D487/04 , C07C275/24 , C07D239/06
摘要： Disclosed is a multi-step process for preparing a compound of Formula I: wherein R1 to R3 are as defined herein. The compounds of formula I inhibit the binding of human intercellular adhesion molecules to the Leukointegrins. As a result, these compounds are useful in the treatment of inflammatory and immune cell-mediated diseases.
摘要翻译：公开了制备式I化合物的多步法：其中R 1至R 3如本文所定义。式I的化合物抑制人细胞间粘附分子与白血球素结合。结果，这些化合物可用于治疗炎性和免疫细胞介导的疾病。

102. 发明授权

US06981263B1 Methods and systems for converged service creation and execution environment applications 失效
标题翻译：融合服务创建和执行环境应用程序的方法和系统
公开(公告)号：US06981263B1
公开(公告)日：2005-12-27
申请号：US09893437
申请日：2001-06-29
申请人： Li Zhang , Jeffrey P. Cassanova , Robert B. Collicott
发明人： Li Zhang , Jeffrey P. Cassanova , Robert B. Collicott
IPC分类号： G06F15/163 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06027 , G06Q50/188 , H04L65/1009 , H04L65/1043 , H04L65/4007 , H04L65/403 , H04L67/14 , H04L67/16
摘要： Embodiments of the present invention relate to systems and methods for a converged service creation and execution application. In an embodiment, an application is coupled to an application server. One or more open application programming interfaces are coupled to the application server, and service session management logic is also coupled to the application server.
摘要翻译：本发明的实施例涉及用于融合服务创建和执行应用的系统和方法。在一个实施例中，应用耦合到应用服务器。一个或多个开放的应用编程接口耦合到应用服务器，并且服务会话管理逻辑也耦合到应用服务器。

103. 发明授权

US06953576B2 Method of modulating tumor immunity 失效
标题翻译：调节肿瘤免疫的方法
公开(公告)号：US06953576B2
公开(公告)日：2005-10-11
申请号：US09933131
申请日：2001-08-21
申请人： Li Zhang , Kevin Young
发明人： Li Zhang , Kevin Young
IPC分类号： A61K35/12 , A61K35/17 , A61K38/17 , A61K38/19 , A61K39/00 , A01N63/00 , A61K35/26 , C12N5/00
CPC分类号： A61K38/19 , A61K35/17 , A61K38/1709 , A61K39/0011 , A61K2039/5158 , C12N5/0637 , C12N2501/2302 , C12N2501/2304
摘要： Novel cells and molecules involved in tumor immunity are disclosed. The novel cells are regulatory T-cells having the phenotype CD3+αβ-TcR+CD4−CD8−CD44−CD28−NK1.1−. The regulatory cells express Ly6A and osteopontin while non-regulatory cells do not.
摘要翻译：公开了涉及肿瘤免疫的新型细胞和分子。这些新型细胞是具有表型CD3 + SUPER + CD3A-TcR + CD4 + CD8 + CD44的调节性T细胞 CD28 - NK1.1 。调节细胞表达Ly6A和骨桥蛋白，而非调节细胞则不表达。

104. 发明申请

US20050169942A1 Novel DNA sequences of the botulinum neurotoxin complex of Clostridium botulinum type A-Hall (Allergan) strain for production of therapeutics 审中-公开
标题翻译：肉毒梭菌型A-Hall（Allergan）菌株的肉毒杆菌神经毒素复合物的新型DNA序列用于治疗药物的生产
公开(公告)号：US20050169942A1
公开(公告)日：2005-08-04
申请号：US10961935
申请日：2004-10-07
申请人： Shengwen Li , Li Zhang , Kei Aoki , Wei-Jen Lin
发明人： Shengwen Li , Li Zhang , Kei Aoki , Wei-Jen Lin
IPC分类号： A61K39/08 , C07H21/04 , C07K14/195 , C07K14/33 , C12N20060101 , C12N1/21 , C12N15/74
CPC分类号： C07K14/33
摘要： This invention broadly relates to recombinant DNA technology, molecular biology, neuroscience, and medicine. Particularly, the present invention features novel sequences of the toxin and non-toxin components of the Clostridium botulinum toxin type A-Hall (Allergan) strain complex as well as the expression vector system in a heterologous organism and methods to express such nucleic acid sequences.
摘要翻译：本发明广泛涉及重组DNA技术，分子生物学，神经科学和医学。特别地，本发明的特征在于肉毒杆菌毒素A型霍尔（Allergan）菌株复合物的毒素和非毒素组分的新型序列以及异源生物体中的表达载体系统和表达该核酸序列的方法。

105. 发明申请

US20050083998A1 Data demodulation for a CDMA communication system 有权
标题翻译： CDMA通信系统的数据解调
公开(公告)号：US20050083998A1
公开(公告)日：2005-04-21
申请号：US10688145
申请日：2003-10-17
申请人： Tao Li , Li Zhang
发明人： Tao Li , Li Zhang
IPC分类号： H04J11/00 , H04B1/707
CPC分类号： H04B1/707 , H04B2201/70707 , H04J13/0044 , H04J13/12
摘要： An integrated circuit that performs data demodulation on partially despread symbols includes a despreading unit, a channel compensation unit, and a symbol combiner. The despreading unit despreads input samples and provides despread symbols for a first code channel with a first spreading factor. The channel compensation unit multiplies the despread symbols with channel estimates and provides demodulated symbols. The symbol combiner combines groups of demodulated symbols to obtain recovered data symbols for a second code channel with a second spreading factor that is an integer multiple of the first spreading factor. The channel compensation and symbol combining are dependent on whether or not transmit diversity is used. For a TDM design, despread symbols for multiple first code channels are processed in a TDM manner, one channel at a time, to obtain recovered data symbols for multiple second code channels. The channel compensation unit and symbol combiner can be operated in a pipelined manner.
摘要翻译：对部分解扩符号执行数据解调的集成电路包括解扩单元，信道补偿单元和符号组合器。解扩单元对输入样本进行解扩，并为具有第一扩频因子的第一码信道提供解扩符号。信道补偿单元将解扩符号与信道估计相乘，并提供解调符号。符号组合器组合解调符号组，以获得具有作为第一扩频因子的整数倍的第二扩展因子的第二码信道的恢复数据符号。信道补偿和符号组合取决于是否使用发射分集。对于TDM设计，针对多个第一代码信道的解扩符号以TDM方式一次处理一个信道，以获得多个第二代码信道的恢复数据符号。信道补偿单元和符号组合器可以以流水线方式操作。

106. 发明授权

US06615341B2 Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control 有权
公开(公告)号：US06615341B2
公开(公告)日：2003-09-02
申请号：US09876189
申请日：2001-06-05
申请人： Gilbert C. Sih , Qiuzhen Zou , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee , Charles E. Sakamaki , Prashant A. Kantak , Sanjay K. Jha , Jian Lin
发明人： Gilbert C. Sih , Qiuzhen Zou , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee , Charles E. Sakamaki , Prashant A. Kantak , Sanjay K. Jha , Jian Lin
IPC分类号： G06F9302
CPC分类号： G06F9/3816 , G06F9/30014 , G06F9/30098 , G06F9/30149 , G06F9/30152 , G06F9/3885 , G06F15/7857
摘要： A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

107. 发明授权

US06425070B1 Variable length instruction decoder 失效
标题翻译：可变长度指令解码器
公开(公告)号：US06425070B1
公开(公告)日：2002-07-23
申请号：US09044086
申请日：1998-03-18
申请人： Qiuzhen Zou , Gilbert C. Sih , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee
发明人： Qiuzhen Zou , Gilbert C. Sih , Inyup Kang , Quaeed Motiwala , Deepu John , Li Zhang , Haitao Zhang , Way-Shing Lee
IPC分类号： G06F9302
CPC分类号： G06F9/3816 , G06F9/30014 , G06F9/30098 , G06F9/30149 , G06F9/30152 , G06F9/3885 , G06F15/7857
摘要： The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.
摘要翻译：本发明是用于数字信号处理的新颖且改进的方法和电路。本发明的一个方面要求使用可变长度指令集。可变长度指令的一部分可以存储在存储器空间内的相邻位置，同时跨越存储器字边界的指令的开始和结束。此外，通过使指令包含可变数量的指令片段来实现本发明的附加方面。每个指令片段导致执行特定操作或操作，允许在每个时钟周期期间进行多个操作。因此，在每个时钟周期期间执行多个操作，减少执行任务所需的总时钟周期数。示例性DSP包括一组三个数据总线，数据可以通过该数据总线与寄存器组和三个数据存储器交换。使用两条以上的数据总线，特别是三条数据总线，实现了本发明的另一方面，这显着减少了总线竞争。本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。宽总线耦合到宽数据存储器，并且两个窄总线耦合到两个窄数据存储器。通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。这允许通过多个处理单元对特定数据集执行多个操作，而不向存储器读取和写入数据。本发明的示例性实施例中的处理单元包括算术逻辑（ALU）和乘法累加（MAC）单元。当结合使用多总线架构，高度并行指令或两者时，实现本发明的另一方面，其中执行高度流水线化，多操作的处理。

108. 发明授权

US5679228A Electrodialysis including filled cell electrodialysis (electrodeionization) 失效
标题翻译：电渗析包括填充细胞电渗析（电去离子）
公开(公告)号：US5679228A
公开(公告)日：1997-10-21
申请号：US571403
申请日：1995-12-13
申请人： Irving D. Elyanow , Wayne A. McRae , Keith J. Sims , Li Zhang
发明人： Irving D. Elyanow , Wayne A. McRae , Keith J. Sims , Li Zhang
IPC分类号： A23C9/144 , B01D61/44 , B01D61/46 , B01D61/48 , B01D61/58 , B01J47/08 , C01B11/04 , C01B11/06 , C02F1/42 , C02F1/44 , C02F1/467 , C02F1/469 , C02F9/00
CPC分类号： A23C9/144 , B01D61/44 , B01D61/48 , B01D61/58 , B01J47/08 , C01B11/04 , C01B11/06 , C02F1/441 , C02F1/469 , B01D61/025 , B01D61/027 , B01D61/145 , B01D61/147 , B01D61/422 , C02F1/42 , C02F1/44 , C02F1/4674 , C02F1/4693 , C02F1/4695 , C02F2101/163 , C02F2201/46115 , C02F9/00
摘要： Improved electrodialysis (ED) stacks are disclosed having one or more components selected from the group: a) cation exchange membranes having ion exchange groups predominantly sulfonic acid groups and a minor amount of weakly acidic and/or weakly basic groups or membranes which are selective to monovalent cations and simultaneously therewith, cation exchange granules selective to monovalent cations as packing in the dilute compartments; b) anion exchange membranes having as ion exchange groups only quaternary ammonium and/or quaternary phosphonium groups and substantially no primary, secondary and/or tertiary amine and/or phosphine groups or membranes which are selective to monovalent anions simultaneously therewith, anion exchange granules selective to monovalent anions as packing in the dilute compartments; c) as packing in the dilute compartment, anion exchange granules which are selective to monovalent anions, or cation exchange granules which are selective to monovalent cations, or cation exchange granules having as exchange groups a predominant amount of sulfonic acid groups and a minor amount of weakly acidic and/or weakly basic groups, or anion exchange granules consisting of organic polymers having as anion exchange groups only quaternary ammonium and/or quaternary phosphonium groups and almost no primary, secondary and/or tertiary amine and/or phosphine groups.
摘要翻译：公开了改进的电渗析（ED）堆叠，其具有一个或多个选自以下的组分：a）具有主要为磺酸基团的离子交换基团和少量弱酸性和/或弱碱性基团或膜的阳离子交换膜，一价阳离子，同时具有选择性的阳离子交换颗粒，作为填充在稀室中的一价阳离子; b）具有作为离子交换基团的离子交换基团的阴离子交换膜仅具有季铵和/或季鏻基团，并且基本上不具有与单价阴离子同时选择性的伯，仲和/或叔胺和/或膦基或膜，阴离子交换颗粒选择性作为包装在稀释室中的单价阴离子; c）作为稀释室中的填料，对单价阴离子有选择性的阴离子交换颗粒，或对一价阳离子有选择性的阳离子交换颗粒，或具有主要量的磺酸基和交替基团的阳离子交换颗粒，弱酸性和/或弱碱性基团或由具有阴离子交换基团的有机聚合物组成的阴离子交换颗粒仅为季铵和/或季鏻基团，并且几乎不具有伯，仲和/或叔胺和/或膦基团。

109. 发明授权

US5644156A Porous silicon photo-device capable of photoelectric conversion 失效
标题翻译：多孔硅光电器件能够进行光电转换
公开(公告)号：US5644156A
公开(公告)日：1997-07-01
申请号：US420515
申请日：1995-04-12
申请人： Taketoshi Suzuki , Tadashi Sakai , Li Zhang , Taijun Murakami
发明人： Taketoshi Suzuki , Tadashi Sakai , Li Zhang , Taijun Murakami
IPC分类号： H05B33/10 , H01L29/16 , H01L29/47 , H01L31/028 , H01L31/173 , H01L31/18 , H01L33/34 , H01L33/42 , H05B33/12 , H05B33/22 , H01L27/095 , H01L29/812 , H01L31/07
CPC分类号： H01L33/346 , H01L29/16 , H01L29/47 , H01L31/0284 , H01L31/173 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A semiconductor device includes a porous silicon layer with an impurity concentration of 1.times.10.sup.19 to 1.times.10.sup.21 cm.sup.-3, in which a plurality of pores are formed, and a thermal oxide film 0.01 to 10 .mu.m thick formed on the expanded surfaces of the porous silicon layer, wherein said expanded surfaces include internal surface of said pores.
摘要翻译：半导体器件包括杂质浓度为1×10 19至1×10 21 cm -3的多孔硅层，其中形成多个孔，并且形成在多孔硅层的扩展表面上的厚度为0.01至10μm的热氧化膜，其中所述扩展表面包括所述孔的内表面。

110. 发明授权

US12043952B2 Electric steam iron 有权
公开(公告)号：US12043952B2
公开(公告)日：2024-07-23
申请号：US18102894
申请日：2023-01-30
申请人： Li Zhang
发明人： Li Zhang
IPC分类号： D06F75/16 , D06F75/20 , D06F75/24 , D06F75/26
CPC分类号： D06F75/16 , D06F75/20 , D06F75/24 , D06F75/265
摘要： The present disclosure provides an electric steam iron, comprising: a housing provided with a water injection unit, the water injection unit being configured to injecting water; a heating unit comprising a heating shell and a heating element, a first chamber and a second chamber being set in the heating shell, the first chamber is configured for receiving water from the water injection unit; the heating shell is in the first chamber and heats the water in the first chamber to generate steam; the second chamber is connected with the first chamber to receive steam in the first chamber; a first lead-out hole is defined in a bottom of the first chamber; a cover is provided to cover a bottom of the heating shell a steam ironing plate, a steam channel is on the steam ironing plate, the steam channel being distributed on the steam ironing plate in a roundabout manner.

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