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101. 发明专利

DE10241451A1 未知
公开(公告)号：DE10241451A1
公开(公告)日：2003-04-24
申请号：DE10241451
申请日：2002-09-06
申请人： ELPIDA MEMORY INC
发明人： FUNABA SEIJI , NISHIO YOJI
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C5/06 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/4093 , H03K19/0175 , G11C11/407
摘要： In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.

102. 发明公开

EP2608261A2 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：EP2608261A2
公开(公告)日：2013-06-26
申请号：EP12196671.7
申请日：2012-12-12
申请人： Elpida Memory, Inc.
发明人： Nakazawa, Shigeyuki , Ishikawa, Toru
IPC分类号： H01L25/065 , H01L23/48 , H01L23/58
CPC分类号： H01L23/5226 , G11C5/063 , G11C29/025 , G11C29/1201 , H01L22/34 , H01L23/481 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06596
摘要： Disclosed herein is a semiconductor chip that includes:
a plurality of penetration electrodes (15) each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and
a third penetration electrode; and a wiring (18) configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode.
摘要翻译：所述半导体芯片包括：贯穿所述半导体芯片的主表面与背表面之间的多个贯通电极（15），所述贯通电极包括多个第一贯穿电极，第二贯穿电极和第三贯穿电极; 以及配置成与多个区域相交的布线（18），每个区域被限定为相应的两个第一穿透电极之间的区域，布线的一端耦合到第二穿透电极，另一端该导线连接到第三穿透电极。

103. 发明公开

EP2575140A1 Semiconductor chip, semiconductor device, and method of measuring the same 有权转让
标题翻译： Halbleiterchip，Halbleiterbauelement und Messverfahrendafür
公开(公告)号：EP2575140A1
公开(公告)日：2013-04-03
申请号：EP12185045.7
申请日：2012-09-19
申请人： Elpida Memory, Inc.
发明人： Ishikawa, Toru , Segawa, Machio
IPC分类号： G11C29/02 , H01L25/065
摘要： In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.
摘要翻译：在其中堆叠具有多个信号TSV的半导体芯片的半导体器件中，需要大量的工时来对每个信号TSV执行连续性测试。根据本发明，直接对信号TSV进行连续性测试。除了信号TSV之外还布置了虚设的凸块。当半导体芯片堆叠时，半导体芯片的虚设凸块通过导电路径连接，导电路径可以通过半导体芯片之间的虚设凸块一行。导电路径的连续性测试允许测量和检测两个堆叠的半导体芯片的接合表面上的接合缺陷。

104. 发明公开

EP2565929A2 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译： Halbleiterbauelement和Verfahren zu seiner Herstellung
公开(公告)号：EP2565929A2
公开(公告)日：2013-03-06
申请号：EP12179171.9
申请日：2012-08-03
申请人： Elpida Memory, Inc.
发明人： Saino, Kanta
IPC分类号： H01L29/51 , H01L29/78 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/51 , H01L21/28044 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device comprises an MIS field effect transistor including a channel region made of p-conductive silicon, a gate insulating film including a first insulating film having dielectric constant higher than dielectric constant of silicon dioxide, and a gate electrode. The gate electrode includes a first metal film formed on the gate insulating film and having a work function greater than a work function of intrinsic semiconductor silicon, and a p-conductive silicon film formed on the first metal film and in contact with the first metal film.
摘要翻译：一种半导体器件包括：MIS场效应晶体管，包括由p导电硅制成的沟道区;栅极绝缘膜，包括介电常数高于二氧化硅介电常数的第一绝缘膜;以及栅电极。栅电极包括形成在栅绝缘膜上并具有大于本征半导体硅的功函数的功函数的第一金属膜和形成在第一金属膜上并与第一金属膜接触的p导电硅膜。

105. 发明公开

EP2555237A2 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：EP2555237A2
公开(公告)日：2013-02-06
申请号：EP12176678.6
申请日：2012-07-17
申请人： Elpida Memory, Inc.
发明人： Kitano, Tomohiro , Nagamine, Hisayuki
IPC分类号： H01L23/522 , H01L27/02
CPC分类号： H01L23/5226 , H01L21/563 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/5223 , H01L23/5225 , H01L23/528 , H01L25/0657 , H01L25/18 , H01L27/0207 , H01L27/10897 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/15311
摘要： A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.
摘要翻译：一种半导体装置，其特征在于，具有：第1外部端子，具有第1尺寸;多个第2外部端子，具有比所述第1尺寸小的第2尺寸;第1外部端子和第2外部端子排列的外部端子区域; 多条导线连接在第二外部端子和形成在外部端子区域附近并对应于第二外部端子的多个电路之间。第二外部端子和导线构成多个接口。每个接口包括至少一个调整部分，其调整导线的时间常数，使得导线具有相同的时间常数。至少一部分调整部分位于在外部端子区域中由第一尺寸和第二尺寸之间的差异产生的边缘区域中。

106. 发明公开

EP2535848A2 Communication device and semiconductor chip 审中-公开
标题翻译： Kommunikationsvorrichtung und Halbleiterchip
公开(公告)号：EP2535848A2
公开(公告)日：2012-12-19
申请号：EP12171796.1
申请日：2012-06-13
申请人： Elpida Memory, Inc.
发明人： Taguchi, Masao
IPC分类号： G06K19/073
CPC分类号： G06K19/07345
摘要： A device includes a first substrate that has a first antenna having a first loop and second loop that form loop shapes viewed in a planar projection; and a second substrate that has a second antenna having a third loop and fourth loop that form loop shapes viewed in the planar projection. The first substrate and the second substrate are disposed so that the first antenna and the second antenna face each other. At least when the first substrate and the second substrate operate, the first antenna and the second antenna are in a state that the first antenna and the second antenna are capable of being magnetically coupled.
摘要翻译：一种器件包括第一衬底，其具有第一天线，其具有第一环和第二环，所述第一环形成在平面投影中观察的环形形状; 以及具有第二天线的第二基板，所述第二天线具有在所述平面投影中观察的形成环形的第三环和第四环。第一基板和第二基板被布置成使得第一天线和第二天线彼此面对。至少当第一基板和第二基板工作时，第一天线和第二天线处于第一天线和第二天线能够被磁耦合的状态。

107. 发明公开

EP2149842A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：EP2149842A1
公开(公告)日：2010-02-03
申请号：EP08752131.6
申请日：2008-04-25
申请人： Elpida Memory, Inc.
发明人： MIURA, Seiji , HARAGUCHI, Yoshinori , ABE, Kazuhiko , KANEKO, Shoji
IPC分类号： G06F12/06 , G06F12/00 , G06F13/16
CPC分类号： G11C14/00 , G06F13/4243 , G11C16/30
摘要： The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
摘要翻译：本发明的目的在于提供一种能够确保存储容量的可扩展性的高速，低成本且用户友好的信息处理系统。信息处理系统被配置为包括信息处理设备，易失性存储器和非易失性存储器。通过将信息处理装置，易失性存储器和非易失性存储器串联连接并减少连接信号的数量，可以在保持存储容量的可扩展性的同时提高处理速度。当将非易失性存储器的数据传输到易失性存储器时，执行纠错，从而提高可靠性。包括多个芯片的信息处理系统被配置为信息处理系统模块，在该信息处理系统模块中芯片被交替地堆叠和布置，并且通过球栅阵列（BGA）或通过芯片之间的接合来布线。

108. 发明公开

EP1246202A3 Semiconductor memory device 审中-公开
公开(公告)号：EP1246202A3
公开(公告)日：2007-01-10
申请号：EP02011953.3
申请日：1999-03-03
申请人： Elpida Memory, Inc.
发明人： Tsuchiya, Tomohiro, c/o NEC Corporation
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： A semiconductor device is disclosed that includes blocks (101-104) having normal cell arrays and redundant cell arrays. An R/N switchover setting circuit (140) includes, in one embodiment, a plurality of normally conducting transistors arranged in series. A redundancy determination circuit (120) receives an address and determines whether or not a redundancy cell array is to be used. When a redundancy cell array is to be used, the redundancy determination circuit (120) outputs not only an active YPR signal, but also the current column-wise position of the defective cell array. The position information is applied to the switchover setting circuit (140) through a redundancy position decoder (130). The switchover setting circuit (140) generates switching signals DSW based on the received column positions, and outputs the signals to the R/N switching circuit (150). The switching circuit (150) switches and connects, on the basis of the received signals, the I/O lines of an input/output section to selected normal cell arrays and a redundant cell array, bypassing the defective cell array.

109. 发明公开

EP2584563A3 Memory device in particular extra array configured therein for configuration and redundancy information 审中-公开
标题翻译：存储装置中，特别是与用于配置和冗余信息的在其中附加地被配置排列
公开(公告)号：EP2584563A3
公开(公告)日：2014-09-10
申请号：EP12182293.6
申请日：2012-08-30
申请人： Elpida Memory, Inc.
发明人： Bartoli, Simone , Pagliato, Maruo , Mina, Diego Della
IPC分类号： G11C29/00
CPC分类号： G11C29/789
摘要： Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second ward lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.

110. 发明公开

EP2575134A3 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：EP2575134A3
公开(公告)日：2013-07-03
申请号：EP12186309.6
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Shido, Taihei , Dono, Chiaki , Kondo, Chikara , Miyazaki, Shinya
IPC分类号： G11C7/10 , G11C11/4096 , G06F12/00
CPC分类号： G06F12/00 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C11/4096
摘要： Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits.
摘要翻译：本文公开了一种设备，该设备包括分别发送多个连续的第一数据比特的第一数据线，分别发送多个连续的第二数据比特的第二数据线和分别发送多个连续的第三数据比特的第三数据线的设备 BOC电路根据地址信息重新排列从多条第一数据线提供的多个第一数据位的顺序，BOC电路将结果提供给多条第二数据线作为多个第二数据位，以及a DBI电路根据预定条件彼此独立地对从多个第二数据线提供的多个第二数据位进行反相或非反转，DBI电路将结果作为多个第三数据线提供给多个的第三数据位。

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