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101. 发明申请

WO2020079429A1 FORMATION OF CORRELATED ELECTRON MATERIAL (CEM) DEVICES WITH RESTORED SIDEWALL REGIONS 审中-公开
公开(公告)号：WO2020079429A1
公开(公告)日：2020-04-23
申请号：PCT/GB2019/052948
申请日：2019-10-16
申请人： ARM LIMITED
发明人： BESSER, Paul Raymond , HE, Ming , CELINSKA, Jolanta Bozena
IPC分类号： H01L45/00
摘要： Subject matter disclosed herein relates to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch (300) includes removing of an exposed portion of a CEM film (170) to form an exposed sidewall region (174) bordering a remaining unexposed portion of the CEM film under or beneath a conductive overlay (160). The method further includes at least partially restoring properties of the exposed sidewall region to a CEM via exposure of the exposed sidewall region to one or more gaseous annealing agents.

102. 发明申请

WO2020053570A1 COMPARISON OF A VOLTAGE SIGNAL TO A REFERENCE 审中-公开
公开(公告)号：WO2020053570A1
公开(公告)日：2020-03-19
申请号：PCT/GB2019/052517
申请日：2019-09-10
申请人： ARM LIMITED
发明人： LABBE, Benoit , SAVANTH, Parameshwarappa Anand Kumar , MYERS, James Edward
IPC分类号： G06F1/28 , H03K3/00
摘要： Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example,which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power.

103. 发明申请

WO2020044036A1 METHOD AND APPARATUS FOR COHERENT INTERCONNECT RECOVERY WITH PROTOCOL LAYER RE-TRANSMISSION 审中-公开
公开(公告)号：WO2020044036A1
公开(公告)日：2020-03-05
申请号：PCT/GB2019/052400
申请日：2019-08-28
申请人： ARM LIMITED
发明人： XU, Zheng , JALAL, Jamshed
IPC分类号： H04L1/16 , G06F12/0831 , G06F13/36 , H04L1/00
摘要： A fault tolerant data processing network includes a number of nodes intercoupled through an interconnect circuit. The micro-architectures of the nodes are configured for sending and receiving messages via the interconnect circuit. In operation, a first Request Node sends a read request to a Home Node. In response, the Home Node initiates transmission of the requested data to the first Request Node. When the first Request Node detects that a fault has occurred, it sends a negative-acknowledgement message to the first Home Node. In response, the Home Node again initiates transmission of the requested data to the first Request Node. The requested data may be transmitted from a local cache of a second Request Node or transmitted by a Slave Node after being retrieved from a memory. The data may be transmitted to the first Request Node via the Home Node or directly via the interconnect.

104. 发明申请

WO2020044015A1 SYSTEM, METHOD AND APPARATUS FOR COMPUTATIONALLY EFFICIENT DATA MANIPULATION 审中-公开
公开(公告)号：WO2020044015A1
公开(公告)日：2020-03-05
申请号：PCT/GB2019/052269
申请日：2019-08-12
申请人： ARM LIMITED
发明人： WHATMOUGH, Paul Nicholas , MATTINA, Matthew , LIU, Zhigang
IPC分类号： G06N3/063 , G06F17/16 , G06F17/15
摘要： A system, apparatus and method for exposing input data operands and input weight operands to elements of a two-dimensional array so that two pairs of operands are exposed to each element of the array.

105. 发明申请

WO2020039168A1 SWITCHED SOURCE LINES FOR MEMORY APPLICATIONS 审中-公开
公开(公告)号：WO2020039168A1
公开(公告)日：2020-02-27
申请号：PCT/GB2019/052270
申请日：2019-08-13
申请人： ARM LIMITED
发明人： JELOKA, Supreet , PRABHAT, Pranay , MYERS, James Edward
IPC分类号： G11C11/418 , G11C11/419 , G11C16/08 , G11C16/26
摘要： Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.

106. 发明申请

WO2019243785A1 COMPILABLE DATA MODEL 审中-公开
公开(公告)号：WO2019243785A1
公开(公告)日：2019-12-26
申请号：PCT/GB2019/051675
申请日：2019-06-17
申请人： ARM IP LIMITED
发明人： FRY, John Ronald
IPC分类号： G06F16/2455
摘要： A technology is provided for controlling input to a data digest model compiler in a data digest system, comprising: parsing a descriptor of a data structure, data content arranged in compliance with the data structure being operable to be emitted by a physical data source device; restructuring a parsed the data structure descriptor according to a constrained data paradigm into a formal structure descriptor acceptable by the data digest model compiler as an input to generate a compiled executable operable to process the data content; augmenting the formal structure descriptor with processing directives operable to cause runtime transformation of at least one data content portion of the data structure into a predetermined input parameter form acceptable by a compiled executable generated by the data digest model compiler; and inputting the formal structure descriptor augmented with the processing directives as a data digest model to the data digest model compiler to generate the compiled executable.

107. 发明申请

WO2019202064A1 POWER RAIL NOISE MONITORING TO DETECT ATTEMPTED SECURITY TAMPERING OR SIDE CHANNEL ATTACKS 审中-公开
公开(公告)号：WO2019202064A1
公开(公告)日：2019-10-24
申请号：PCT/EP2019/060057
申请日：2019-04-18
申请人： ARM LIMITED
发明人： VINCENT, Hugo John Martin , DAS, Shidhartha , MERIAC, Milosch , TENENTES, Vasileios
IPC分类号： G06F21/75 , G01R31/08 , H04L9/00 , G01R19/00 , G01R29/26 , G01R19/165
摘要： An apparatus and method for detecting a change in electrical properties in a system is disclosed. Embodiments of the disclosure enable the detection of a change in electrical properties in a system by, in response to a load generated on a power delivery network power in at least part of the system, measuring noise induced in the power delivery network in response to the load. Based on the measured noise, a dynamic-response property of the power delivery network is determined and the dynamic-response property is compared to a stored reference dynamic-response property of the power delivery network based on a predetermined load. In the event of a difference between the dynamic-response property and the reference dynamic-response property, a response to the event is triggered to indicate tampering with the power delivery network.

108. 发明申请

WO2019180427A1 BIB, BIB SYSTEM AND METHOD OF USE OF BIB SYSTEM 审中-公开
公开(公告)号：WO2019180427A1
公开(公告)日：2019-09-26
申请号：PCT/GB2019/050774
申请日：2019-03-20
申请人： UNSWORTH, Jennifer Claire
发明人： UNSWORTH, Jennifer Claire
IPC分类号： A41B13/10
摘要： A bib (10) comprising a body portion (12), a neck portion (14) located at an upper portion (38) of the body portion (12), and a first adhesive portion (16) located at a lower portion (36) of the body portion (12).

109. 发明申请

WO2019102189A1 MULTI-TIER CACHE PLACEMENT MECHANISM 审中-公开
公开(公告)号：WO2019102189A1
公开(公告)日：2019-05-31
申请号：PCT/GB2018/053361
申请日：2018-11-20
申请人： ARM LIMITED
发明人： WANG, Jiajun , RAMRAKHYANI, Prakash S. , WANG, Wei , ELSASSER, Wendy Arnott
IPC分类号： G06F12/0888 , G06F12/0811 , G06F12/0862
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0862 , G06F12/0888 , G06F2212/1008 , G06F2212/1021 , G06F2212/608
摘要： Storage of data in a cache system is controlled by a cache monitor. A cache line is filled in response to a memory instruction from a cache client. The cache monitor includes a predictor table and update logic. An entry in the predictor table comprises an instruction identifier that associates the entry with a memory instruction and, for each cache in the system, a reuse counter. The update logic is configured to update a reuse counter table dependent upon cache behavior in response to memory instructions. Storage of data a first data address in cache in response to a memory instruction having a first instruction identifier, is dependent upon reuse counter values in an entry of the predictor table associated with first instruction identifier. Reuse counters are updated dependent upon cache behavior. A Bloom filter or other data structure may be used to associate data addresses with a memory instruction.

110. 发明申请

WO2019097223A1 TRACKING DEVICE, SYSTEM AND METHOD 审中-公开
公开(公告)号：WO2019097223A1
公开(公告)日：2019-05-23
申请号：PCT/GB2018/053295
申请日：2018-11-14
申请人： EIGHT19 LIMITED
发明人： WRIGHT, Guy Michael , SELE, Christoph Wilhelm , MARINELLI, Claudio
IPC分类号： G01S5/02 , H04W64/00
摘要： Broadly speaking, the present techniques relate to an apparatus, a system and a method for tracking entities in an environment.

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