专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

101. 发明公开

EP1662660A2 Method and apparatus for providing compensation against temperature, process and supply voltage variation 审中-公开
标题翻译：用于补偿针对温度，电压和制造变化的方法和装置
公开(公告)号：EP1662660A2
公开(公告)日：2006-05-31
申请号：EP05025953.0
申请日：2005-11-29
申请人： STMicroelectronics Pvt. Ltd
发明人： Gupta, Sushil Kumar , Garg, Paras
IPC分类号： H03K19/003
CPC分类号： H03K3/011 , H03K3/3565 , H03K17/145 , H03K19/00384
摘要： In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.
摘要翻译：在本发明的装置和方法，用于提供相对于温度，工艺和MOS电路的电源电压变化补偿已经提出。本发明提供在过程中，温度和电压检测电路，其控制体偏置并在CMOS电路中的器件的驱动的变化。检测电路是独立的要被控制的CMOS电路中的任何输入或内部信号。

102. 发明公开

EP1641129A1 An improved turbo encoder 审中-公开
标题翻译： Verbesserter Turbo Kodierer
公开(公告)号：EP1641129A1
公开(公告)日：2006-03-29
申请号：EP05108777.3
申请日：2005-09-22
申请人： STMicroelectronics Pvt. Ltd
发明人： Soogoori, Shashi Kiran rao
IPC分类号： H03M13/29
CPC分类号： H03M13/2903 , H03M13/2957
摘要： An improved turbo encoder comprising multiple interleaved parallel concatenated recursive systematic convolutional encoder wherein each recursive systematic convolutional encoder is provided with an LUT that simultaneously provides the output bit pattern as well as the next state value corresponding to a defined set of multiple input bits and present state for operating said recursive systematic convolutional encoder. Thus the approach works with improved LUTs, which do the job of both puncturing and multiplexing for four input bits at a time. Theoretically the proposed approach works almost four times faster than the conventional approach, which can handle only one input bit at a time.
摘要翻译：一种改进的turbo编码器，包括多个交错并行级联递归系统卷积编码器，其中每个递归系统卷积编码器都具有一个LUT，该LUT同时提供输出位模式以及与定义的一组多个输入位对应的下一个状态值和当前状态用于操作所述递归系统卷积编码器。因此，该方法适用于改进的LUT，它们一次对四个输入位进行打孔和多路复用。理论上，所提出的方法比常规方法快几乎四倍，这种方法一次只能处理一个输入位。

103. 发明公开

EP1538533A3 Improved FFT/IFFT processor 审中-公开
标题翻译：改进的FFT / IFFT处理器
公开(公告)号：EP1538533A3
公开(公告)日：2006-02-22
申请号：EP04106295.1
申请日：2004-12-03
申请人： STMicroelectronics Pvt. Ltd
发明人： Saha, Kaushik , Maiti, Srijib Narayan , Cornero, Marco
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： An improved FFT / IFFT processor comprising computation means capable of processing butterfly operations, and storage means for storing the operands of butterfly operations, and a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations, and wherein the computation means is capable of simultaneously accessing and processing said multiple butterfly operations.

104. 发明公开

EP1624704A2 Video decoder with parallel processors for decoding macro-blocks 有权转让
标题翻译： Videodekoder mit Parallelprozessorenfürdie Dekodierung von Makroblocks
公开(公告)号：EP1624704A2
公开(公告)日：2006-02-08
申请号：EP05016383.1
申请日：2005-07-28
申请人： STMicroelectronics Pvt. Ltd
发明人： Saha, Kaushik , Sarkar, Abhik , Maiti, Srijib Narayan
IPC分类号： H04N7/50 , G06T9/00
CPC分类号： H04N19/436 , H04N19/433 , H04N19/44 , H04N19/51 , H04N19/61
摘要： A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.
摘要翻译：在并行处理环境中的视频解码器的宏块级并行实现，包括可变长度解码（VLD）块，以解码编码的离散余弦变换（DCT）系数; 接收所述解码的离散余弦变换（DCT）系数的主节点; 以及用于在宏块级别并行实现逆离散余弦变换（IDCT）和运动补偿的多个从属节点/处理器。

105. 发明公开

EP1359588A3 Memory architecture for increased speed and reduced power consumption 审中-公开
标题翻译：存储器体系结构具有改进的速度和降低功耗
公开(公告)号：EP1359588A3
公开(公告)日：2005-11-30
申请号：EP03009612.7
申请日：2003-04-29
申请人： STMicroelectronics Pvt. Ltd
发明人： Nautiyal, Vivek , Kumar, Ashish
IPC分类号： G11C8/14 , G11C7/18
CPC分类号： G11C7/18 , G11C8/14
摘要： An improved multi-wordline memory architecture providing decreased bitline coupling for increased speed and reduced power consumption comprising an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

106. 发明公开

EP1553676A1 An electronic protection device 审中-公开
标题翻译： ElektronischesSchutzgerät
公开(公告)号：EP1553676A1
公开(公告)日：2005-07-13
申请号：EP04290064.7
申请日：2004-01-09
申请人： STMicroelectronics S.A. , STMicroelectronics Pvt. Ltd
发明人： Shah, Hitesh , Charvet, Pierre
IPC分类号： H02H3/24 , G06F1/30
CPC分类号： G06F1/30
摘要： This invention relates to an electronic protection device.
According to the invention, this protection device disables the output from a digital circuit whenever an input signal is below a threshold voltage level and comprises :

a threshold voltage detector, and
a gating means for enabling/disabling the output from the digital circuit, having its control input connected to the output of the threshold voltage detector.
摘要翻译：本发明涉及一种电子保护装置。根据本发明，每当输入信号低于阈值电压电平时，该保护装置禁止来自数字电路的输出，并且包括：阈值电压检测器和用于使能/禁止数字电路的输出的门控装置电路，其控制输入连接到阈值电压检测器的输出。

107. 发明公开

EP1443650A2 Method and system for reducing power consumption in digital circuit using charge redistribution circuits 审中-公开
标题翻译：用于减少与Ladungsneuverteilungschaltungen数字电路的功耗的方法和设备
公开(公告)号：EP1443650A2
公开(公告)日：2004-08-04
申请号：EP04001539.8
申请日：2004-01-26
申请人： STMicroelectronics Pvt. Ltd
发明人： Nautiyal, Vivek , Kumar, Ashish
IPC分类号： H03K19/00
CPC分类号： G11C5/063 , H03K19/0019
摘要： A method and system for reducing power consumption in digital circuits using charge redistribution, comprising a plurality of signal lines, an intermediate floating virtual source / sink, and a charge redistribution circuit connected to each said signal line that isolates said line from its source and connects it to the intermediate floating virtual source / sink during an idle period prior to a change of state.
This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary line.
摘要翻译：一种用于使用电荷再分配减少数字电路的功耗，包括的信号线。多个中间浮动虚源/汇的方法和系统，以及连接到每个所述信号线的电荷重新分布电路的确从它的源和所连接隔离所述线它的中间浮动虚源/在状态变化之前，空闲期间下沉。这种电荷再分配提供由于电荷循环不插入额外的免费在线稳态统计独立的优势。

108. 发明公开

EP1304804A2 Fractional divider 审中-公开
标题翻译： Teiler mit gebrochenemTeilverhältnis
公开(公告)号：EP1304804A2
公开(公告)日：2003-04-23
申请号：EP02022060.4
申请日：2002-10-02
申请人： STMicroelectronics Pvt. Ltd
发明人： Chakravarthy, Kalyana
IPC分类号： H03K23/68 , H03K23/66
CPC分类号： H03L7/1976 , H03K23/68
摘要： An improved fractional divider that provides high resolution without the need for any analog components. It comprises an integer value storage means containing the integer part of the division value 'K' connected to the input of a programmable counter means that is configured for a count value of 'K' or 'K+1' depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces said count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.
摘要翻译：改进的分数分频器，提供高分辨率，无需任何模拟组件。它包括整数值存储装置，其包含连接到可编程计数器装置的输入的除法值“K”的整数部分，该可编程计数器装置被配置为计数值“K”或“K + 1”，这取决于一个计数控制信号，并且产生输出信号以及终端计数信号，该终端计数信号连接到分数累加器装置的使能输入，该分数累加器装置在加法溢出时产生所述计数控制信号，并且具有连接到其结果输出的第一输入和第二输入连接到分数值存储装置的输出，包含分频值的小数部分。

109. 发明公开

EP1303048A1 An improved switched-capacitor based charge redistribution successive approximation analog to digital converter (ADC) 审中-公开
标题翻译：到数字转换器的模拟与渐变和开关电容器
公开(公告)号：EP1303048A1
公开(公告)日：2003-04-16
申请号：EP02021533.1
申请日：2002-09-26
申请人： STMicroelectronics Pvt. Ltd
发明人： Nandy, Tapas
IPC分类号： H03M1/38
CPC分类号： H03M1/0854 , H03M1/468 , H03M1/804
摘要： This invention relates to an improved binary-weighted, switched-capacitor, charge-redistribution successive approximation Analog-to-Digital Converter (ADC) characterized in that it includes an adjusting mechanism for adding a charge corresponding to one-half of the Least Significant Bit (LSB) of said ADC to the charge stored in the switched capacitor array after the sampling phase of said ADC so as to provide a quantization error that is evenly distributed between +0.5 LSB and -0.5 LSB, without the need for any additional processing clock cycles.
摘要翻译：一种改进的二进制加权，开关电容，电荷再分配的逐次逼近模拟 - 数字转换器（ADC）可以包括在调整机构，用于将电荷对应于所述ADC的所述至少显著位（LSB）的一半存储在电容器阵列ADC的切换采样阶段之后其上的电荷。这样做是为了提供一个量化误差也±0.5倍之间均匀分布的LSB，而无需任何附加的处理时钟周期。

110. 发明公开

EP3439298A1 TRANSMITTER CIRCUIT AND METHOD FOR DIGITAL SATELLITE EQUIPMENT CONTROL 有权转让
公开(公告)号：EP3439298A1
公开(公告)日：2019-02-06
申请号：EP17188532.0
申请日：2017-08-30
申请人： STMicroelectronics International N.V. , STMicroelectronics Pvt. Ltd.
发明人： DASGUPTA, Nabarun
IPC分类号： H04N7/20 , H04N21/61 , H03K17/12
摘要： Satellite controller circuitry includes a connection (i.e. coaxial or single wire with ground), with a control unit (108) receiving a data message and generating a response message as output, and transmitter circuitry (110) transmitting the response message. The transmitter circuitry (110) has a first transistor having a first conduction terminal coupled to the connection (100), a second conduction terminal coupled to ground, and a control terminal coupled to receive output from the control unit (108), a second transistor having a first conduction terminal coupled to the connection (100), a second conduction terminal coupled to ground, and a control terminal coupled to receive the output from the control unit (108). The first and second transistors are configured such that a second current flowing through the first conduction terminal of the second transistor is in a non-unity ratioed relationship, or in a unity ratioed relationship, with a first current flowing through the first conduction terminal of the first transistor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式