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    • 91. 发明专利
    • CIRCULATING SHIFT REGISTER INCREMENTER/DECREMENTER
    • GB1527438A
    • 1978-10-04
    • GB2164876
    • 1976-05-25
    • HEWLETT PACKARD CO
    • G04G99/00G06F7/493G06F7/504G06F7/508G11C19/00H03K27/00G06F15/20G04C3/00G06F7/385
    • 1527438 Electronic timepieces HEWLETT PACKARD CO 25 May 1976 [14 July 1975] 21648/76 Heading G3T [Also in Division G4] A circuit for incrementing or decrementing time data, in binary-coded-decimal form, in a circulating shift-register memory includes a flip-flop 10, and gates, as shown, receiving input data at I and providing output data at O. A first control signal A causes complementing of each bit during which it is 1; a second control signal B causes incrementing or decrementing when it is 0 or 1 respectively, and a third control signal C pre-sets flip-flop 10 during the first (least significant) bit of a digit which is to be incremented or decremented. Control signal C provides the necessary carries. When the 0À01 seconds digit is incremented from 9 (1001), control signal A complements the most significant bit and control signals B and C cause decrementing to provide the digit 0, a carry being provided to the 0À1 seconds digit. When the tens of minutes digit is incremented from 5 (0101), control signal A complements the second most significant bit , decrementing is carried out and a carry is provided to the hours digit. Appropriate action is taken for the other digits for a 12-hour or 24-hour clock mode. Decrementing may be carried out to count down from a pre-set time; when zero is reached an alarm signal may be provided or incrementing may then be started.
    • 99. 发明授权
    • Transmission system, transmission apparatus, and clock synchronization method
    • 传输系统,传输设备和时钟同步方法
    • US09344266B2
    • 2016-05-17
    • US14613443
    • 2015-02-04
    • FUJITSU LIMITED
    • Ryuji KayamaHiroyuki SuzukiTakashi NakanoNobuyuki KobayashiAkira NozawaKoji Suda
    • H04L7/00H03K27/00
    • H04L7/0016H04J3/0641
    • A transmission system includes: a first transmission apparatus to distribute a synchronization clock; and one or more second transmission apparatuses each to connect to the first transmission apparatus so as to synchronize with the synchronization clock from the first transmission apparatus, the second transmission apparatus including: a selection portion to select the first or second transmission apparatus of a connection destination so as to switch the synchronization clock; an output portion to generate an inquiry signal addressed to the first transmission apparatus via the second transmission apparatus of the connection destination selected; a determination portion to determine whether or not the inquiry signal generated by the second transmission apparatus is received; and a second control portion to determine that there is a synchronization clock loop having a loop path through the second transmission apparatus of the connection destination when the determination portion receives the inquiry signal.
    • 传输系统包括:第一发送装置,用于分配同步时钟; 以及一个或多个第二传输设备,每个连接到第一传输设备以与来自第一传输设备的同步时钟同步,第二传输设备包括:选择部分,用于选择连接目的地的第一或第二传输设备 以切换同步时钟; 输出部,经由所选择的连接目的地的第二发送装置生成寻址到第一发送装置的查询信号; 确定部分,用于确定是否接收到由第二传输装置产生的查询信号; 以及第二控制部分,当确定部分接收到查询信号时,确定存在具有通过连接目的地的第二传输装置的环路径的同步时钟环路。
    • 100. 发明授权
    • Data and clock recovery circuit
    • 数据和时钟恢复电路
    • US5483180A
    • 1996-01-09
    • US346206
    • 1994-11-22
    • Sang-Hoon ChaiMun-Yang ParkMyung-Shin KwakHae-Wook Choi
    • Sang-Hoon ChaiMun-Yang ParkMyung-Shin KwakHae-Wook Choi
    • H03K27/00H03L7/087H03L7/089H03L7/14H04J3/06H04L7/00H04L7/033H03K5/13
    • H03L7/087H03L7/14H04J3/0688H04L7/0083H03L7/0891H04L7/033
    • Disclosed is a data and clock recovery circuit possible to restore data signals and synchronizing clocks which have been distorted during transmission over the communication line, which is comprised of the following: main oscillation loop that maintains operating frequency by using the input data and a self oscillation loop that operates using reference clock embedded within multiplex communication devices when communication lines get shorted or when power is restored after an outage; loop selecting switch which selects the main oscillation loop during normal operating mode and selects the self oscillation loop when communication line shorts or when the power is being restored; data signal monitor which connects to the loop selecting switch and determines communication line shorting by monitoring data transmission; power supply monitor which connects to the loop selecting switch and monitors the restoration of power after an outage. The circuit maintains stable operation and supplies stable output to multiplex communication devices not only during the normal operating conditions, but also when there is a communication line shorting or restoration of power after a power supply outage.
    • 公开了一种数据和时钟恢复电路,可以恢复通过通信线路传输期间已经失真的数据信号和同步时钟,其包括以下:通过使用输入数据和自振荡来维持工作频率的主振荡环路 环路,当通信线路短路或停电后恢复供电时,使用嵌入多路通信设备内的参考时钟进行工作; 环路选择开关,其在正常操作模式下选择主振荡环路,并且当通信线路短路或电源恢复时选择自振荡环路; 数据信号监视器,连接到环路选择开关,通过监视数据传输确定通信线路短路; 电源监视器,连接到回路选择开关,并监视停电后的电源恢复。 该电路不仅在正常工作条件下,而且在电源中断后还有通信线路短路或恢复供电时,保持稳定运行,并提供稳定的输出以多路复用通信设备。