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    • 91. 发明申请
    • DATA SWITCHING APPARATUS
    • 数据切换装置
    • WO99009715A1
    • 1999-02-25
    • PCT/GB1998/002138
    • 1998-07-17
    • H04L12/931H04L12/935H04L12/937H04L12/56
    • H04L49/254H04L49/20H04L49/30
    • Data switching apparatus for a digital data transmission system includes user interface means (12) operable to connect external users (11) to the apparatus. Routing means (13) is operable to determine, from control information received with data from a source user, the destination to which the data should be sent. The routing means (13) includes means for separating the control information from the data. A switching matrix (17) is operable to set up connection between the source user and the destination user and master control means (18) operable to control the operation of the switching matrix (17).
    • 用于数字数据传输系统的数据交换设备包括可操作以将外部用户(11)连接到设备的用户接口装置(12)。 路由装置(13)可操作以从从源用户的数据接收的控制信息中确定应发送数据的目的地。 路由装置(13)包括用于从控制信息与数据分离的装置。 交换矩阵(17)可操作以建立源用户和目的地用户之间的连接以及可操作以控制交换矩阵(17)的操作的主控制装置(18)。
    • 93. 发明申请
    • ATM SWITCH WITH VC PRIORITY BUFFERS
    • ATM开关与VC优先缓冲区
    • WO1997013346A1
    • 1997-04-10
    • PCT/US1996015737
    • 1996-10-02
    • GENERAL DATACOMM, INC.JONES, Trevor
    • GENERAL DATACOMM, INC.
    • H04L12/56
    • H04L49/30H04L49/1523H04L49/20H04L49/3009H04L49/3081H04L49/508H04L49/552H04L2012/5651H04L2012/5679H04L2012/5681
    • An ATM switch (10) has a plurality of link controllers (12) each having a FIFO (30) for each VC established and a FIFO (32) for each priority level. Cells are pushed into the VC FIFO (30) and a pointer to the VC FIFO (30) is pushed into an arbitration FIFO (32) for the priority level of the VC FIFO (30). The arbitration FIFOs (32) are examined according to a schedule and cells are popped up from VC FIFOs (30) according to priority for exit from the controller (12). According to one embodiment, the highest priority arbitration FIFO (32a) is always examined first and none of the lower priority arbitration FIFOs (32b-32d) are examined unless the highest priority arbitration FIFO is empty. According to another embodiment, timers are set for the lower priority arbitration FIFOs (32b-32d) and if a timer expires for a lower priority arbitration FIFO, it is examined.
    • ATM交换机(10)具有多个链路控制器(12),每个链路控制器具有用于每个建立的VC的FIFO(30)和用于每个优先级的FIFO(32)。 单元被推入VC FIFO(30),并且指向VC FIFO(30)的指针被推入用于VC FIFO(30)的优先级的仲裁FIFO(32)。 根据调度检查仲裁FIFO(32),并且根据从控制器(12)退出的优先级,从VC FIFO(30)弹出单元。 根据一个实施例,始终检查最高优先权仲裁FIFO(32a),并且除非最高优先权仲裁FIFO为空,否则不检查低优先权仲裁FIFO(32b-32d)。 根据另一个实施例,针对较低优先权的仲裁FIFO(32b-32d)设置定时器,并且如果针对较低优先权的仲裁FIFO的定时器期满,则对其进行检查。