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91. 发明公开

EP2122830A2 A CLOCK CIRCUIT 有权
标题翻译： TAKTSCHALTUNG
公开(公告)号：EP2122830A2
公开(公告)日：2009-11-25
申请号：EP08716768.0
申请日：2008-02-07
申请人： TEXAS INSTRUMENTS LIMITED
发明人： LYTOLLIS, Shaun
IPC分类号： H03K21/08 , H03L7/18
CPC分类号： H03K21/08 , G06F1/06 , H03K21/40 , H03K23/68 , H03L7/0995
摘要： A clock circuit with a plurality of inputs for a plurality of respective clock signals, the clock signals alternating between a first and a second state. At least one divider circuit is arranged to take an input clock signal and provide an output that is in the first state for a first fixed multiple of the duration the clock signal is in the first state, and in the second state for a second fixed multiple of the duration the clock signal is in the second state. A plurality of delay circuits are arranged to take the output of the divider circuit or circuits and provide a set of outputs each delayed by a fixed duration. A selection circuit is arranged to select the outputs of the delay circuits in sequence. The selection circuit is arranged to select the next output in the sequence at or after the time when the selected output changes from the first state to the second state.

92. 发明公开

EP1710915A4 IF COUNTING METHOD 审中-公开
标题翻译： ZF-ZÄHLVERFAHREN
公开(公告)号：EP1710915A4
公开(公告)日：2007-01-10
申请号：EP05709238
申请日：2005-01-07
申请人： TOYOTA JIDOSHOKKI KK , NIIGATA SEIMITSU CO LTD
发明人： GOTO S , MIYAGI HIROSHI
IPC分类号： G01R23/15 , H03J7/28 , H03K21/40
CPC分类号： H03K21/40
摘要： There is provided an IF counting method for realizing an IF counter having a smaller circuit configuration. The IF counter includes: a down-count type IF counting unit (1) for counting IF signals which have been divided; an IF counting period generation unit (2) for generating a period for counting the IF signals; an IF count upper limit value preset unit (3) for giving an initial value of a count start; a lower m-bit comparator (5) for comparing the information on the lower m bits of the count value to the information set in the upper/lower limit value difference preset unit; and a judgment unit (6) for judging whether the count value is within a predetermined range according to the information on the upper n+1-m bits of the count value and the information on the comparison result by the lower m-bit comparator (5).

93. 发明公开

EP1630963A2 Anordnung und Verfahren zum Ermitteln, ob der Zählstand eines Zählers einen vorbestimmten Zählstand erreicht hat oder nicht 审中-公开
标题翻译：装置和方法用于确定计数器的计数是否已经达到预定的计数或不
公开(公告)号：EP1630963A2
公开(公告)日：2006-03-01
申请号：EP05111666.3
申请日：2000-03-01
申请人： Infineon Technologies AG
发明人： Rohm, Peter , Leteinturier, Patrick
IPC分类号： H03K21/00 , H03K21/40
CPC分类号： H03K21/00 , H03K21/40
摘要： Die beschriebene Anordnung und das beschriebene Verfahren zeichnen sich dadurch aus, daß die Ermittlung durch Variieren der bei der Ermittlung zu berücksichtigenden Bits der zu vergleichenden Zählstände konfigurierbar ist. Dadurch kann die Ermittlung mit minimalem Aufwand jederzeit individuell an verschiedene oder wechselnde Bedürfnisse angepaßt werden.
摘要翻译：该装置是通过改变一个时间窗口的位置和/或尺寸可配置的确定过程中被考虑和/或改变所述计数器的状态的位的确定期间被考虑在内。因此独立claimsoft包括用于确定性采矿是否计数器已经达到限定的计数或不的方法。

94. 发明授权

EP1234283B1 VERFAHREN UND ANORDNUNG ZUM BETREIBEN EINES MEHRSTUFIGEN ZÄHLERS IN EINER ZÄHLRICHTUNG 有权
标题翻译： VERFAHREN UND ANORDNUNG ZUM BETREIBEN EINES MEHRSTUFIGENZÄHLERSIN EERERZÄHLRICHTUNG
公开(公告)号：EP1234283B1
公开(公告)日：2004-06-09
申请号：EP00993194.0
申请日：2000-11-27
申请人： Infineon Technologies AG
发明人： ALLINGER, Robert , POCKRANDT, Wolfgang
IPC分类号： G07F7/10 , H03K21/40
CPC分类号： G07F7/1008 , G06Q20/341 , G07F7/082 , G07F7/0866 , H03K21/40
摘要： The invention relates to a method for operating a multistage counter in only one counting direction. The inventive method comprises the following steps: changing the count value of a single-stage auxiliary counter that can only be changed in one counting direction, whereby count value states of the multi-stage counter are predetermined, detecting the respective count value states of the multi-stage counter and the single-stage auxiliary counter and producing first authenticity data by linking the count value of the auxiliary counter to additional data.
摘要翻译：本发明涉及仅在一个计数方向上操作多级计数器的方法。本发明的方法包括以下步骤：改变只能在一个计数方向上改变的单级辅助计数器的计数值，由此预定多级计数器的计数值状态，检测该计数值的各个计数值状态多级计数器和单级辅助计数器，并通过将辅助计数器的计数值链接到附加数据来产生第一真实性数据。

95. 发明授权

EP1082816B1 VERFAHREN UND ANORDNUNG ZUM BETREIBEN EINES MEHRSTUFIGEN ZÄHLERS IN EINER ZÄHLRICHTUNG 有权
标题翻译：方法和系统的操作多级逆流IN A计数方向
公开(公告)号：EP1082816B1
公开(公告)日：2004-01-02
申请号：EP99936340.1
申请日：1999-05-28
申请人： Infineon Technologies AG
发明人： ALLINGER, Robert , HOLLFELDER, Robert , POCKRANDT, Wolfgang , WEDEL, Armin
IPC分类号： H03K21/40 , G07F7/10
CPC分类号： G07F7/1008 , G06Q20/341 , G07F7/082 , H03K21/40
摘要： The invention relates to a method for operating a multi-stage counter (11) in one counting direction only, comprising the following steps: altering the count value of a single-stage counter (1) which can only be altered in one direction when the multi-stage counter (11) reaches certain predetermined count value states; detecting the particular count value states of the multi-stage counter (11) and the single-stage auxiliary counter (1); comparing the values of the count value states of the single-stage counter (1) and the multi-stage counter (11) which were detected; and producing an indicator signal based on the results of this comparison.

96. 发明公开

EP1294100A2 Method and apparatus for providing resampling function in a modulus prescaler of a frequency source 审中-公开
标题翻译：在einem中的Verfahren und Vorrichtungfüreine Neuabtastung Frequenzvorteiler
公开(公告)号：EP1294100A2
公开(公告)日：2003-03-19
申请号：EP02256053.6
申请日：2002-08-30
申请人： Nokia Corporation
发明人： Salmi, Mika , Svard, Mikael
IPC分类号： H03K21/08
CPC分类号： H03K21/40 , H03K21/08 , H03L7/193
摘要： A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit (10). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF 18) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers (12, 14, 16) need not be increased in an effort to reduce the prescaler noise., thereby conserving current in battery powered and other applications.
摘要翻译：重采样技术用于降低噪声并提高预分频器电路输出中的信号质量（10）。使用由从预分频器的输入获得的信号计时的至少一个触发器（FF）（例如，D型FF18）来实现最后一个分频器级的输出的重新采样。这可以减少或消除由预分频器的输出中的边沿抖动引起的噪声，以及预分频器产生的杂散信号的影响。这些教导可用于整数N个PLL和分数N个PLL，以及单个和可编程的双模或多模预分频器。使用这种技术，不必增加预分频器分频器（12,14,16）的电流消耗，以减少预分频器噪声，从而节省电池供电和其他应用中的电流。

97. 发明公开

EP1157468A1 ANORDNUNG UND VERFAHREN ZUM ERMITTELN, OB DER ZÄHLSTAND EINES ZÄHLERS EINEN VORBESTIMMTEN ZÄHLSTAND ERREICHT HAT ODER NICHT 有权
标题翻译：设备和方法，用于判定该计数的计数器规定的计数值达到HAS OR NOT
公开(公告)号：EP1157468A1
公开(公告)日：2001-11-28
申请号：EP00916776.8
申请日：2000-03-01
申请人： Infineon Technologies AG
发明人： ROHM, Peter , LETEINTURIER, Patrick
IPC分类号： H03K21/00 , H03K21/40
CPC分类号： H03K21/00 , H03K21/40
摘要： The inventive system and method is characterized in that the method of detection can be configured by varying the size and/or the position of a time slot to be taken into consideration for the detection and/or by varying the relevant bits of the counts to be compared. The invention makes it possible to individually adapt the detection method to various or varying requirements at any time and with a minimum of expenditure required.

98. 发明授权

EP0746109B1 Diviseur de fréquence programmable rapide 失效转让
标题翻译：更快的可编程分频器
公开(公告)号：EP0746109B1
公开(公告)日：2000-11-15
申请号：EP96410059.8
申请日：1996-05-28
申请人： STMicroelectronics S.A.
发明人： Colavin, Osvaldo
IPC分类号： H03K23/66 , H03K21/40
CPC分类号： H03K23/66 , H03K21/40

99. 发明授权

EP0162605B1 Sequential selection circuits 有权
标题翻译：顺序选择电路
公开(公告)号：EP0162605B1
公开(公告)日：1990-06-20
申请号：EP85302931.2
申请日：1985-04-25
申请人： SONY CORPORATION
发明人： Shionoya,Toshio c/o Sony Corporation
IPC分类号： G09G3/28 , H03K5/153 , H03K5/26 , H04N3/14
CPC分类号： G09G3/296 , G09G3/293 , H03K5/15093 , H03K21/40

100. 发明公开

EP0162605A1 Sequential selection circuits 有权
标题翻译： Sequentielle Auswahlschaltungen。
公开(公告)号：EP0162605A1
公开(公告)日：1985-11-27
申请号：EP85302931.2
申请日：1985-04-25
申请人： SONY CORPORATION
发明人： Shionoya,Toshio c/o Sony Corporation
IPC分类号： G09G3/28 , H03K5/153 , H03K5/26 , H04N3/14
CPC分类号： G09G3/296 , G09G3/293 , H03K5/15093 , H03K21/40
摘要： @ A sequential selection circuit for selecting a series of circuits, elements, electrodes or other items over a long period, to activate them sequentially one by one for a short period, comprises a shift register (10) which has a number of shift stages corresponding to the total number that is to be selected for sequentially shifting a single input pulse in response to clock pulses (H) corresponding to the short period. A counter (11) counts the clock pulses (H) so as to generate a pulse output (Pi when a count reaches the total selection number. An input circuit (G1,G2.G3) generates an input pulse (V,) for the shift register (10) in accordance with the pulse output (P) from the counter (11) and a pulse (V) corresponding to the long period. A reset circuit (G1) resets the counter (11) in accordance with the clock pulse (H) and the pulse (V) corresponding to the long period. With such arrangement, when the pulse (V) corresponding to the long period is not generated, the counter (11) will not operate and an effective input pulse (V,) to the shift register (10) will not be generated. Therefore, the shift register (10) will not sequentially read erroneous inputs and a plurality of shift stage outputs will not be generated at the same time. In this manner, the selected circuits, elements, electrodes or other items and drive circuitry and a power supply will be prevented from being damaged.
摘要翻译：一种用于长时间选择一系列电路，元件，电极或其他物品的顺序选择电路，用于在短时间内逐个激活它们，包括移位寄存器（10），其具有对应于响应于对应于短周期的时钟脉冲（H），顺序移位单个输入脉冲而被选择的总数。当计数达到总选择数时，计数器（11）对时钟脉冲（H）进行计数，以产生脉冲输出（P）。输入电路（G1，G2，G3）根据来自计数器（11）的脉冲输出（P）和对应于长周期的脉冲（V）产生用于移位寄存器（10）的输入脉冲（V1）。复位电路（G1）根据时钟脉冲（H）和对应于长周期的脉冲（V）来重置计数器（11）。通过这样的配置，当不产生对应于长周期的脉冲（V）时，计数器（11）将不工作，并且不会产生对移位寄存器（10）的有效输入脉冲（V1）。因此，移位寄存器（10）不会顺序地读取错误的输入，并且不会同时产生多个移位级输出。以这种方式，将防止所选择的电路，元件，电极或其它物品以及驱动电路和电源被损坏。

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